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wideband if receiver subsystem data sheet AD6676 features high instantaneous dynamic range noise figure (nf) as low as 13 db noise spectral density (nsd) as low as ?159 dbfs/hz iip3 up to 36.9 dbm with s purious tones AD6676 1 is a highly integrated if subsystem that can digitize radio frequency (rf) bands up to 160 mhz in width centered on an i ntermedia te frequency ( if) of 70 mhz to 450 mhz. unlike traditional nyquist if sampling adcs, the AD6676 relies on a tunable band - pass - adc with a high oversampling ratio to eliminate the need for band specific if saw filters and gain stages, resulting in significant simplification of the wideband radio receiver architecture. on - chip quadrature digital downconversion followed by selectable dec imation filters reduces the complex data rate to a manageable rate between 62.5 msps to 266.7 msps. the 16 - bit complex output data is transferred to the host via a single or dual lane jesd204b interface supporting line rates of up to 5.333 gbps. functio nal block diagram l? l+ resetb vddio agc4, agc3 agc2, agc1 vdd2nv vssa vdd2 vddd vssd spi csb sclk sdio sdo serdout0+ serdout0? serdout1+ serdout1? vddhsi syncinb sysref agc support clock generation ?2.0v reg jesd204b serializer tx outputs mx m = 12, 16, 24, 32 i q qddc + nco i q band-pass - adc vin? vin+ 27db attenuator (1db steps) clock synthesizer jesd204b subclass 1 control clk+ clk? vddc vddq AD6676 12348-001 vddl vdd1 vss2out vss2in figure 1. 1 this product is pr otected by u.s. and international patents. rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analo g devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2014 analog devices, inc. all rights reserved. technical support www.analog.com
AD6676 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 product highlights ........................................................................... 3 specifications ..................................................................................... 4 digital high speed serdes specifications .............................. 6 digital cmos input/output specifications ............................. 7 clk to sysref timing diagram ......................................... 7 absolute maximum ratings ............................................................ 8 thermal resistance ...................................................................... 8 esd caution .................................................................................. 8 pin configuration and function descriptions ............................. 9 typical performance characteristics ........................................... 11 nominal performance for if = 115 mhz (direct sampling vhf receiver) ............................................................................ 11 nominal performance for if = 140 mhz (w point - to - point receivers) ..................................................................................... 13 nominal performance for if = 181 mhz (wireless infrastructure receiver) ............................................................. 14 nominal performance for if = 250 mhz and bw = 75 mhz ........................................................................................ 16 nominal performance for if = 350 mhz and bw = 160 mhz ...................................................................................... 18 equivalent circuits ......................................................................... 20 terminology .................................................................................... 21 theory of operation ...................................................................... 22 overview ...................................................................................... 22 band - pass - adc architecture ........................................... 23 - adc configuration considerations ................................ 27 attenuator .................................................................................... 32 clock synthesizer ....................................................................... 34 digital processing blocks .............................................................. 37 digital signal processing path .................................................. 38 agc features and peak detection ........................................... 41 gpio functionality .................................................................... 43 power saving modes .................................................................. 43 introduction to the jesd204b interface ................................. 44 functional overview ................................................................. 46 jesd 204b link establishment ................................................. 46 physical layer input/outputs ................................................... 48 configuring the jesd204b link .............................................. 49 synchronization using sysref ............................................... 50 applications information .............................................................. 51 analog input considerations ................................................... 51 clock input considerations ...................................................... 52 if frequency planning .............................................................. 54 pcb design guideli nes ............................................................. 55 powering the AD6676 ................................................................ 56 AD6676 start - up initialization ................................................ 57 serial port interface (spi) .............................................................. 60 spi register map description .................................................. 60 spi operation ............................................................................. 60 register memory map and details .............................................. 62 register memory map ............................................................... 62 register details ........................................................................... 64 outline dimensions ....................................................................... 86 ordering guide .......................................................................... 86 revision history 10/14 revision 0 : initial version rev. 0 | page 2 of 86
data sheet AD6676 the band - pass - adc of the AD6676 , which operates between 2.0 ghz to 3.2 ghz, provides exceptional instantaneous dynamic range and i nherent antialiasing capability. its in - band frequency response typically maintains better than 1 db pass band flatness with out - of - band peaking better than 0.5 db. an integrated digital peak detector enables the instantaneous signal p ower to be monitored over a wide band (shortly after digitization), thus providing agc capability to cope quickly with large in - band or out - of - band blockers. the AD6676 includes various agc monitoring and control features along with an internal 27 db step attenuator in 1 db steps. a flexible agc port with digital input/output pins allows fast control of the AD6676 on - chip step attenuator and/or updates on the input signal via status flags. these features, along with the high instantaneous dynamic range, can significantly simplify agc imple mentation compared to traditional narrow - band if approaches that often require separate agc capability for rf and if protection. in a ddition to r educing s ystem c omplexity, th e AD6676 enables significant s pace a nd p ower c onsumption savings for n ext generation multiple input/multiple output (m imo) receiver architectures. the AD6676 is available in an 8 10 ball array wlcsp p ackage that i s a pproximately 4.3 mm 5.0 mm , w ith a jesd204b s erial interface t hat allows simple i nterfacing to t he host p rocessor. i ts low power c onsumption of 1.2 w compares favorably to if sampling adcs with similar bandwidth and dynamic range capabilities even without considering the added power savings from the elimination of an entire if strip. the AD6676 features multichip synchronization that allows synchronization to within a fraction of an output data sample. for time - domain duplex (tdd) applications, the AD6676 features a fast power - up/power - down mode that further reduces power consumption while still maintaining multichip synchronization. power saving s of up to 60% or 42% is achievable with recovery times of 11.5 s or 2.5 s, depending on the device configuration. auxiliary blocks include an on - chip pll clock multiplier to generate the - adc clock. for applications that require better phase noise pe rformance, an external differential rf clock source may also be used. the spi port programs numerous parameters of the AD6676 , allowin g the device to be optimized for a variety of applications. the AD6676 is available in an 80 - ball wlcsp package with an optimized pin out that enables low cost printed circuit board (pcb) manufacturing. the device operates from a 1.1 v and 2.5 v supply with a total typical power consumption of 1.2 w at 3.2 gsps operation. this product is pr otected by several us patents. contact analog d evices , inc., for further information. product highlights 1. industry leading dynamic range enables high performance, reconfigurable heterodyne (or direct sampling vhf) software defined radios with high agc - free range. 2. continuous time , band - pass - adc supports ifs from 70 mhz to 450 mhz with if signal bandwidths of up to 160 mhz and reduces if filtering requirements. 3. the high insta ntaneous dynamic range and over samplin g si gnificantly of the - adc reduces the if filter complexity . 4. on- chip 27 db digital attenuator with easy to drive resistiv e i nput simplifies interface to rf/if components . 5. small 4 .3 mm 5.0 mm package, simple interface , and integrated d igital attenuator and clock synthesizer save pcb space. 6. low input full - scale level of ? 2 dbm (or less) enabl es 3.3 v rf/if component line ups at reduced p1db and power. 7. fast power saving mode supports tdd protocols. 8. unique profile mode allows the AD6676 to switch between up to four different adc if/bw configurations in 1 s. rev. 0 | page 3 of 86
AD6676 data sheet specifications vdd1 = vddl = vddc = vddq = 1.1 v, vddd = vddhsi = 1.1 v, vdd2 = 2.5 v, vddio = 1.8 v, f if = 250 mhz, bw = 75 mhz, f ad c = 3.2 gh z, attenuator = 0 db, l (inductor values) = 19 nh, maximum pin_0dbfs setting with idac1 fs = 4 ma, f data_iq = 200 msps, s huffler enabled (every clock cycle) with default threshold of 5, unless otherwise noted. table 1 . parameter t emp erature test conditions/comments min typ max unit system dynamic performance full - scale input power level (pin_0dbfs) 1 ? 2 dbm maximum continuous wave ( cw ) input power 2 ?2 ?1 dbfs noise figure (nf) no signal and measured 1 7 db worst in - band noise spectral density full o ver a 5 mhz bandwidth ? 155 ? 152. 5 dbfs/hz noise figure at if center (nf) no signal and measured 1 3 db in - band noise spectral density (nsd) o ver a 5 mhz bandwidth ? 159 dbfs/hz input second - order intercept (ii p 2 ) ?6 dbfs tones 60 dbm second - order i ntermodulation distortion (i md ) (imd2) see table 20 ?68.3 dbc input third - order intercept (iip3) full ?8 dbfs tones 36.9 dbm third - order imd (imd3) full ?8 dbfs tones ? 95 ? 84.2 dbc worst in - band spur for swept cw tone full ? 2 dbfs tone ? 99 ? 93.5 dbfs ? 10 dbfs tone ?10 9.6 dbfs in - band noise full ?2 dbfs tone ?75. 5 ? 7 3.7 dbfs full no cw tone ?78.5 ? 76.5 dbfs gain variation full 0.5 db if input (vin) inp ut span 0 dbfs 0 db attenuator setting 0.48 v p -p 12 db attenuator setting 1.92 v p -p common - mode input voltage self biased 1.0 v differential input impedance 25c 60||2 ? ||pf common - mode input impedance 25c 3.5 k? full - scale input power adjustment (pin_0dbfs) idac1 fs span of 1 ma to 4 ma 12 db digital step attenuator (vin) attenuatio n range full 27 db step size full 1 db input return loss full 20 db input return loss variation vs. attenuator setting full 2 db clock input (clk) clock synthesizer disabled frequency range full 2.0 3.2 ghz amplitude range full 0.4 0.8 2.0 v p -p differential input impedance 25c at 3 ghz 86 ||0. 3 ? ||pf common mode impedance 25c at 3 ghz 700 ||0.8 ? ||pf input return loss 25c with 1:2 balun 15 db common - mode voltage 25c self biased 0.70 v clock synthesizer enabled frequency range 3 full 10 320 mhz amplitude range full single - end ed into clk+ 0.4 0.8 1 .0 v p -p clk+ input impedance 25c 1.4||1.0 k ? ||pf minimum slew rate 12 v/s common - mode voltage 25c self biased 0.55 v rev. 0 | page 4 of 86
data sheet AD6676 parameter t emp erature test conditions/comments min typ max unit clock synthesizer phase detector frequency full 10 80 mhz minimum charge pump output curre nt full 0.1 ma maximum charge pump output current full 6.4 ma vco tuning range full 2.94 3.2 ghz - ? adc and digital downconverter resolution full 16 bits clock frequency ( f ad c ) full 2.0 3.2 ghz if center frequency ( f if ) full 70 450 mhz if bandwidth (bw) maximum bw applies to higher f if 0.005 f ad c 0.05 f ad c if pass band gain flatness full f ad c , f if , and bw dependent 1.0 db out - of - band peaking depends on f ad c , f if , and bw 0.5 db alias rejection regions of f ad c f if 51 db fixed decimation factors full 12, 16, 24, 32 nco tuning resolution decimate by 12 or 24 f ad c /3072 decimate by 16 or 32 f ad c /4096 out - of - range recovery time full 52 adc clock cycles (1/ f ad c ) power supply and consumption analog supply voltage vdd1, vddl, vddq, vddc full 1.0725 1.1 1.1275 v vdd2, vdd2nv full 2.4375 2.5 2.5625 v vss2in use on - chip regulator, tie to vss2out ?2.0 v digital supply voltage (vddd) full 1.0725 1.1 1.1275 v jesd204b supply volt age (vddhsi) full 1.0725 1.1 1.1275 v spi interface supply voltage (vddio) full 1.7 1.8 2.5625 v analog supply current i vdd1 + i vddl full 368 397 ma i vddc + i vddq full clk synthesizer disabled 57 68 ma i vddc 4 + i vddq full clk synthesizer e nabled 93 106 ma i vdd2 + i vdd2nv full 145 165 ma digital supply current (i vddd ) full 141 208 ma jesd204b supply current (i vddhsi ) full 164 190 ma spi interface supply current (i vddio ) full 0.4 1 ma power consumption full with clk syn disabled 1.16 1.31 w with clk syn enabled 1.20 1.34 w standby 5 full 0.44 w power - down full 66 177 mw operating temperature range ?40 +85 c 1 extrapolated input power level is measured at the c enter of if pass band that results in a 0 dbfs power level. 2 the overload level of the - adc for a cw tone is guaranteed up to ?2 dbfs back off from full scale but typically exceeds ?1 dbfs. input signals that have a higher peak - to - average ratio (par) than a cw tone (par = 3 db) must apply additional back off ba sed on the difference in par. 3 the clock synthesizer reference divider (register 0x2bb, bits[7:6]) must be set to divide by 4 or by 2 to ensure that its pha se detector frequency remains 40 mhz. 4 f clk = 200 mhz, f ad c = 3.2 ghz. 5 the AD6676 is configured for recovery time of 11.5 s with vss2 generator/ digital data in standby (register 0x15 0 = 0x4 0 ) and low power adc state (register 0x250 = 0x95). rev. 0 | page 5 of 86
AD6676 data sheet digital high speed s erdes specifications vdd1 = vddl = vddc = vddq = 1.1 v, vddd = vddhsi = 1. 1 v, vdd2 = 2.5 v, vddio = 1.8 v, unless otherwise noted. table 2 . parameter symbol temp . min typ max unit high speed serial input/output line rate 1.6668 5.33 3 gbps dual lane data output period or unit interval ui ful l 1/(20 f data_iq ) 1 sec single lane data output period or unit interval ui full 1/(40 f data_iq ) 1 sec data output duty cycle 25c 50 % data valid time 25c 0.78 ui pll lock time 25c 4 s wake - up time (standby) 25c 5 s wake - up time (power- down) 25c 2.5 ms pipeline delay (latency) full 32.3 1/ f data_iq 1 deterministic jitter 25c 9 ps random jitter at 5.333 gbps 25c 0.7 ps rms output rise/fall time 25c 45 ps syncin b falling edge to first k.28 characters 25c 4 multiframes cgs phase k.28 characters duration 25c 1 multiframes digital outputs (serdout0, serdout1) logic compliance full cml differential output voltage vod full 400 750 mv output offset voltage, ansi mode vos full 0.75 vddhsi/2 1.05 v differential termination impedance 25c 100 ? sysref input (sysref) logic compliance lvds/pecl differential input voltage full 0.6 1.2 1.8 v p - p differential input impedance 2 25c 35/2 k?||pf input common - mode voltage 0.8 0.85 2.0 v syncin input (syncinb+, syncinb?) logic compliance 3 cmos/lvds cmos input voltage high v ih 0.65 vddio v cmos input voltage low v il 0.35 vddio v lvds differential input voltage full 0.6 1.2 1.8 v p -p lvds differential input impedance 25c 100||1 ?||pf lvds input common - mode voltage 0.8 0.85 2.0 v lvds input common - mode impedance 25c 1||1 k? ||pf sysref (sysref) timing requirements 4 clock synthesizer disabled setup time t su_sr 25c 0.16 ns hold time t h_sr 25c 0.84 ns clock synthesizer enabled setup time t su_sr 25c 0.5 ns hold time t h_sr 25c 0.5 ns 1 f data_iq corresponds to the complex output dat a rate (that is, f ad c /dec_factor). latency specification also includes adc and digital filters delays . see table 15 2 the sysref input requires an external differential resistor for proper termination. 3 set via register 0x1e7, bit 2, with cmos being the default setting. 4 sysref setup and hold times are defined with respect to the rising sysref edge and rising clock edge. positive setup time leads the clock edge. positive hold time also lags the clock rising edge. note that the hold time takes into consideration that the internal clock signal used to sample sysref operates a t f ad c / 2; thus, sysref must remain high for at least two f ad c clock cycles . rev. 0 | page 6 of 86
data sheet AD6676 clk to sysref timi ng diagram clk+ clk? sysref+ sysref? t su_sr t h_sr 12348-102 figure 2 . serdes clk+ to sysref+ timing digital cmos input/o utput specifications vdd1 = vddl = vddc = vddq = vddd = vddhsi = 1.1 v, vdd2 = 2.5 v, vddio = 1.8 v , unless otherwise noted. table 3 . parameter symbol test condition s/comments min typ max unit cmos input/output levels input voltage high v ih vddio 0.65 v input voltage low v il vddio 0.35 v output voltage high v oh vddio 0.7 v output voltage low v ol 0.4 v input capacitance 1 pf spi t iming see figure 146 , figure 147 , and figure 148 sclk frequency f sclk 25 mhz sclk period t sclk 40 ns sclk pulse wid th high t high 10 ns sclk pulse width low t low 1 0 ns sdio setup time t ds 2 ns sdio hold time t dh 2 ns spi_reset setup time 1 t spi_rst not shown in figure 146 to figure 148 2 ms sclk f alling e dge to sdo valid propagation delay t access 10 ns csb r ising e dge to sdio hi gh -z t z 10 ns csb fall to sclk rise setup time t s 2 ns sclk fall to csb rise hold time t h 2 ns 1 this is the time required after a software or hardwa re reset until spi access is available again. rev. 0 | page 7 of 86
AD6676 data sheet absolute maximum rat ings tabl e 4 . parameter rating vdd1, vddc, vddl, vddq to vssa ? 0.2 v to +1.2 v vdd2 to vssa ? 0.3 v to + 3.0 v vdd2nv to vssa ? 0.3 v to + 3.0 v vss2in, vss2out to vssa ? 2.5 v to +0.3 v vddd, vddhsi to vssd ? 0.2 v to +1.2 v vddio to vssd ? 0.3 v to + 3.0 v vin+, vin? to vssa ? 0.3 v to vdd2 + 0.3 v l+, l? to vssa ? 0.3 v to vdd2 + 0.3 v clk+, clk? to vssa ? 0.3 v to vddc + 0.3 v sysref+, sysref?, serdout0+, serdout0?, serdout1+, serdout1? to vssd ?0.3 v to vddhsi + 0.3 v syncinb+, syncinb? to vssd ?0.3 v to vddio + 0.3 v csb, sdo, sdio, sclk, resetb, agc 1, agc2, agc3, agc4 to vssd ?0.3 v to vddio + 0.3 v normal operating temperature rang e ?40c to +85c maximum junction temperature under bias 125c storage temperature range ? 65c to +150 c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational sect ion of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance typical ja is specified for a 4 - layer printed circuit board (pcb) with a solid ground plane in conformance to jesd51 - 9 2s2p. in addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes reduces the value of ja . table 5 . thermal resistance package type 4.3 mm 5.0 mm wlcsp 26 0.2 4.5 c/w esd caution rev. 0 | page 8 of 86
data sheet AD6676 pin configuration an d function descripti ons vddq vdd1 vssa vdd1 vdd2 l+ l? vssa 1 2 3 4 5 6 7 8 clk+ vdd1 vdd1 vssa vdd1 vdd2 vdd2 vin+ clk? vddc vdd1 vdd1 vssa vdd1 vssa vin? vddc vddc vdd1 vddl vddl vssa vdd1 vssa vssa vssa vssa vssa vssa vssa vdd2 vdd2 vssa vssa vssa vssd vssd vss2in vdd2nv vssa sysref+ vssd vssd vssd vssd resetb vss2out vddio sysref? vssd vddd vddd vddd sdo agc4 agc2 vddhsi vddshi vddd vddd vddd csb agc3 agc1 serdout0? serdout0+ serdout1? serdout1+ syncinb+ syncinb? sclk sdio a b c d e f g h j k 12348-003 figure 3 . pin conf iguration (top view, not to scale) table 6 . pin function descriptions pin no. mnemonic description - adc modulator b8, c8 vin+, vin? analog inputs with nominal 6 0 ? differential input termination. a6, a7 l+, l? analog output s for external inductor. b1, c1 clk+, clk? clock inputs with nominal 100 ? differential input termination. jesd204b interface k1, k2 serdout0?, serdout0+ lane 0 jesd204b digital cml outputs. k3, k4 serdout1?, serdout1+ lane 1 jesd204b digital cml ou tputs. g1, h1 sysref+, sysref? jesd204b sysref inputs. note that th e s e pin s ha ve no differential termination. k5, k6 syncinb+, syncinb? jesd204b cmos or lvds sync inputs. selectable via register 0x1e7, bit 2. default cmos mode uses the syncinb+ pin only. lvds mode has a 100 ? differential termination. cmos input/outputs h7, j7, h8 , j8 agc 1, agc2, agc3, agc4 agc bidirectional inputs/outputs. by default, agc 2 and agc1 are inputs, wh ereas agc4 and agc3 are outputs. if the agc 2 and agc1 pins are unused, connect them to vssd via a 100 k? resistor. j6 csb serial port enable input. active low. k8 sdio serial port input/output. h6 sdo serial port output. k7 sclk serial port input. g6 resetb active low reset input. this pin places digital logic and spi re gisters into a known default state. leave this pin open if unused because it has an internal pull - up resistor. rev. 0 | page 9 of 86
AD6676 data sheet pin no. mnemonic description power supplies g8 vddio digital supply input for cmos input/outputs (1.8 v to 2.5 v). j1, j2 vddhsi digital 1.1 v supply input for the high speed serial interface. h3 to h5, j3 to j5 vddd digital 1.1 v supply input. f4, f5, g2 to g5, h2 vssd digital supply return. a1 vddq analog 1.1 v supply input for the clk synthesizer charge pump and dividers. c2, d1, d2 vddc analog 1.1 v supply input for the clk synthesizer vco. d4, d5 vddl analog 1.1 v supply input for the adc. a2, a4, b2, b3, b5, c3, c4, c6, d3, d7 vdd1 analog 1.1 v supply input for the adc. a5, b6, b7, e7, e8 vdd2 analog 2.5 v supply input. a3, a8, b4, c5, c7, d6, d8, e1 to e6, f1 to f3, f8 vssa analog supply return. negative voltage regulator f7 vdd2nv analog 2.5 v supply input. g7 vss2out internal ?2.0 v supply output. connect this pin to vss2in. f6 vss2in analog ?2.0 v supply input. connect this pin to vss2out. rev. 0 | page 10 of 86
data sheet AD6676 typical performance characteristics n ominal p erformance for if = 115 mh z (d irect s ampling vhf r eceiver ) f if = 115 mhz, bw = 20 mhz, f ad c = 2.4 ghz, attenuator = 0 db, l ext = 100 nh, maximum pin_0dbfs setting, f data_iq = 75 msps, nominal supplies, shuffler enabled (every 4 clock cycles), with default threshold settings, unless otherwise noted . 0.50 ?1.50 ?1.25 ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 80 150 140 130 120 110 100 90 normalized signal transfer function response (dbfs) frequency (mhz) 12348-607 figure 4 . if pass band flatness (includes digital filter) ?153 ?163 ?162 ?161 ?160 ?159 ?158 ?157 ?156 ?155 ?154 105 125 120 115 110 nsd (dbfs/hz) input frequency (mhz) nsd (?1dbfs signal) nsd (no signal) 12348-608 figure 5. nsd with and without full - scale cw at 108 mhz 0 ?130 ?90 ?100 ?110 ?120 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 105 125 120 115 110 amplitude (dbfs/nbw) input frequency (mhz) nbw = 3.4khz if pass band region ?1dbfs at 108mhz 12348-609 figure 6 . spectral plot of if pass band region with 1 dbfs cw at 108 mhz 5 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 0 600 450 300 150 550 400 250 100 500 350 200 50 normalized stf response (dbfs) frequency (mhz) 12348-610 figure 7 . wideband frequency response (before digital filter) ?153 ?163 ?162 ?161 ?160 ?159 ?158 ?157 ?156 ?155 ?154 ?44 ?2 ?5 ?8 ?11 ?14 ?17 ?20 ?23 ?26 ?29 ?32 ?35 ?38 ?41 nsd (dbfs/hz) input power (dbm) pin_0dbfs = ?2.9dbm shuffler disabled shuffle-every-4 th clock 12348-6 1 1 figure 8 . nsd vs . cw input power, cw at 108 mhz (nsd = 10 mhz, bw = 115 mhz) ?85 ?95 ?94 ?93 ?92 ?91 ?90 ?89 ?88 ?87 ?86 ?44 ?2 ?5 ?8 ?11 ?14 ?17 ?20 ?23 ?26 ?29 ?32 ?35 ?38 ?41 ibn (dbfs) input power (dbm) pin_0dbfs = ?2.9dbm shuffler disabled shuffle-every-4 th clock 12348-612 figure 9 . integrat ed in - band noise (ibn) in if pass band region of 10 mhz vs. swept single tone input power with cw at 130 mhz rev. 0 | page 11 of 86
AD6676 data sheet rev. 0 | page 12 of 86 0 ?130 ?90 ?100 ?110 ?120 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 80 90 100 110 120 130 140 150 amplitude (dbfs) input frequency (mhz) if pass band region = 20mhz worst swept spur for ?1dbfs cw at ?3dbm 2 f data-iq clock spur at 150mhz, at ?87dbfs ?1dbfs at 101.6mhz ?111dbfs 12348-613 figure 10. worst spur falling in 75 mhz pass band for swept cw from 77.5 mhz to 152.5 mhz 0 ?130 ?90 ?100 ?110 ?120 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 105 125 120 115 110 amplitude (dbfs/nbw) input frequency (mhz) ?95dbfs ?94dbfs two tones at ?8dbfs (?10.9dbm) at 114mhz and 116mhz nbw = 3.4khz 12348-614 figure 11. two-tone imd performance (f 1 = 114 mhz, f 2 = 116 mhz) worst imd3 (dbfs) input amplitude (dbfs) ?39 ?6?9?12?15 ?18?21 ?24?27?30 ?33?36 ? 80 ?85 ?90 ?95 ?100 ?105 ?110 ?115 ?120 ?125 ?130 12348-615 figure 12. swept two-tone worst imd3 vs. tone input amplitude (f 1 = 113 mhz, f 2 =118 mhz) worst pass band spur (dbfs) input frequency (mhz) 77.5 87.5 97.5 107.5 117.5 127.5 137.5 147.5 152.5 ? 100 ?103 ?106 ?109 ?112 ?115 ?1dbfs ?6dbfs ?12dbfs ?18dbfs 12348-616 figure 13. worst pass band spur with swept cw from 77.5 mhz to 150 mhz, over p in = ?1 dbfs, ?6 dbfs, ?12 dbfs, and ?18 dbfs 0 ?130 ?90 ?100 ?110 ?120 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 105 125 120 115 110 amplitude (dbfs/nbw) input frequency (mhz) ?95dbfs ?95dbfs two tones at ?8dbfs (?10.9dbm) at 108mhz and 110mhz nbw = 3.4khz 12348-617 figure 14. two-tone imd performance (f 1 = 108 mhz, f 2 = 110 mhz) worst imd3 (dbfs) frequency (mhz) 110 135 130 125 120 115 ? 80 ?85 ?90 ?95 ?100 ?105 ?110 ?20dbfs ?14dbfs ?8dbfs 12348-618 figure 15. swept two tone worst imd3 vs. frequency over pass band (?f = 5 mhz for two tones, p in = ?8 dbfs, ?14 dbfs, and ?20 dbfs)
data sheet AD6676 nominal performance for i f = 140 mh z ( w p oint - to - p oint r eceivers ) f if = 140 mhz, bw = 56 mhz or 112 mhz, f ad c = 3.2 ghz, attenuator = 0 d b, l ext = 43 nh, maximum pin_0dbfs setting, f data_iq = 200 msps, nominal supplies, shuffler enabled (every clock cycle), with default threshold settings, unless otherwise noted . 0.5 ?2.0 ?1.5 ?1.0 ?0.5 0 80 200 170 150 130 190 180 160 140 120 110 100 90 normalized stf response (dbfs) frequency (mhz) 56mhz bw setting 112mhz bw setting 12348-619 figure 16 . if pass band flatness (includes digit al filter) nsd (dbfs/hz) input frequency (mhz) 80 90 100 110 120 130 140 150 160 170 180 190 200 ?162 ?160 ?158 ?156 ?154 ?152 ?150 ?148 ?146 ?144 bw setting of 112mhz (ibn = ?72.2dbfs) bw setting of 56mhz (ibn = ?80.5dbfs) 12348-620 figure 17 . nsd with no signal, ibn = 112 mhz and 56 mhz 0 ?90 ?100 ?110 ?120 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 40 240 140 60 160 80 180 100 200 120 220 amplitude (dbfs) input frequency (mhz) nbw = 9.2khz ibn = ?88dbfs 14mhz qam1024 at ?52dbfs cnr = 36db 2.5 ch bw = 35mhz ?19.7dbm cw interferer tone at ?22dbfs 12348-621 figure 18 . spectral plot of cw interferer dynamic range for qam1024, channel bw = 14 mhz at sensitivity level with cw interferer 3 0 db higher at 35 mhz offset 5 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 0 600 450 350 250 550 500 400 300 200 150 100 50 normalized stf response (dbfs) frequency (mhz) 56mhz bw setting 112mhz bw setting 12348-622 figure 19 . wideband frequency response (before digital filter) ?75 ?80 ?85 ?90 ?95 ?44 ?2 ?5 ?8 ?11 ?14 ?17 ?20 ?23 ?26 ?29 ?32 ?35 ?38 ?41 ibn (dbfs) input power (dbm) pin_0dbfs = ?2.7dbm ch bw = 56mhz ch bw = 28mhz ch bw = 14mhz ch bw = 7mhz 12348-623 figure 20 . ibn vs. swept single tone input power over channel bw = 7 mhz, 14 mhz, 28 mhz, and 56 mhz, cw blocker at 350 mhz 0 ?90 ?100 ?110 ?120 ?130 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 amplitude (dbfs) input frequency (mhz) nbw = 9.6khz two tones at ?8dbfs (?10.7dbm) at 137.5mhz and 142.5mhz 115 120 125 130 135 140 145 150 155 160 165 ?101dbfs ?100dbfs 12348-624 figure 21 . two - ton e imd performance (f 1 = 137.5 mhz, f 2 = 142.5 mhz) rev. 0 | page 13 of 86
AD6676 data sheet rev. 0 | page 14 of 86 nominal performance for if = 181 mhz (wireless infrastructure receiver) f if = 181 mhz, bw = 75 mhz, f adc = 2.94912 ghz, attenuator = 0 db, l ext = 43 nh, maximum pin_0dbfs setting, f data_iq = 122.88 msps, shuffler enabled (every clock cycle), with default threshold settings, unless otherwise noted. 0.50 ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 140 145 150 155 160 165 170 175 180 185 190 195 200 205 210 220215 normalized stf response (dbfs) frequency (mhz) 12348-625 figure 22. if pass band flatness (includes digital filter) nsd (dbfs/hz) input frequency (mhz) 145 155 165 175 185 195 205 215 ?160 ? 150 ?151 ?152 ?153 ?154 ?155 ?156 ?157 ?158 ?159 nsd (?1dbfs signal) nsd (no signal) 12348-626 figure 23. nsd with and without full-scale cw at 210 mhz 0 ?90 ?100 ?110 ?120 ?130 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 amplitude (dbfs/nbw) input frequency (mhz) nbw = 5.6khz ?1dbfs (?3.5dbm) at 220mhz 140 150 160 170 180 190 200 210 220 225 75mhz if pass band region 12348-627 figure 24. spectral plot of if pass band region with ?1 dbfs cw at 220 mhz 5 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 0600 450 350 250 550500 400 300 20015010050 normalized stf response (dbfs) frequency (mhz) 12348-628 figure 25. wideband frequency response (before digital filter) ? 152 ?153 ?154 ?155 ?156 ?157 ?158 ?159 ?160 ?161 ?162 ?44 ?2?5?8?11?14 ?17?20 ?23?26?29 ?32?35 ?38?41 nsd (dbfs) input power (dbm) pin_0dbfs = ?2.5dbm 143.5mhz 143.5mhz 181mhz 12348-629 figure 26. nsd vs. cw input power, cw = 210 mhz (nsd = 5 mhz, bw = 146 mhz, 181 mhz, and 216 mhz band edges) ? 75.0 ?75.5 ?76.0 ?76.5 ?77.0 ?77.5 ?78.0 ?78.5 ?79.0 ?79.5 ?80.0 ?44 ?2?5?8?11?14 ?17?20 ?23?26?29 ?32?35 ?38?41 ibn (dbfs) input power (dbm) pin_0dbfs = ?2.5dbm 12348-630 figure 27. ibn in if pass band region (bw = 75 mhz) vs. swept single tone input power with cw at 220 mhz
data sheet AD6676 0 ?130 ?90 ?100 ?110 ?120 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 125 135 145 155 165 175 185 195 205 215 225 235 amplitude (dbfs/nbw) input frequency (mhz) worst swept pass band spur for ?1dbfs cw at ?3.5dbm if pass band region = 75mhz ?97dbfs nbw = 5.6khz ?1dbfs at 185mhz 12348-631 figure 28 . worst spur falling in 75 mhz pass band for swept cw from 122.88 mhz to 245.76 mhz 0 ?130 ?90 ?100 ?110 ?120 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 145 155 165 175 185 195 205 215 amplitude (dbfs/nbw) input frequency (mhz) ?96dbfs ?94dbfs nbw = 5.6khz two tones at ?8dbfs (?10.5dbm) at 178.5mhz and 183.5mhz 12348-632 figure 29 . two - tone imd performance (f 1 = 178.5 mhz, f 2 = 183.5 mhz) worst imd3 (dbfs) input amplitude (dbfs) ?39 ?6 ?9 ?12 ?15 ?18 ?21 ?24 ?27 ?30 ?33 ?36 ?80 ?85 ?90 ?95 ?100 ?105 ?110 ?115 ?120 ?125 ?130 12348-633 figure 30 . swept two - tone worst imd3 vs . tone level (dbfs) (f 1 = 178.5 mhz, f 2 = 183.5 mhz) ?94 ?97 ?100 ?103 ?106 ?109 ?112 ?115 worst pass band spur (dbfs) input frequency (mhz) 125 145 165 185 205 225 245 ?1dbfs ?6dbfs ?12dbfs ?18dbfs 12348-634 figure 31 . s wept worst pass band spur with cw swept from 122.88 mhz to 245.76 mhz, over p in = 1 dbfs, 6 dbfs, 12 dbfs, and 18 dbfs 0 ?130 ?90 ?100 ?110 ?120 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 145 155 165 175 185 195 205 215 amplitude (dbfs/nbw) input frequency (mhz) ?90dbfs ?92dbfs nbw = 5.6khz two tones at ?8dbfs (?10.5dbm) at 169mhz and 193mhz 12348-635 figure 32 . two - tone imd performance (f 1 = 169 mhz, f 2 = 193 mhz) worst imd3 (dbfs) frequency (mhz) 140 150 160 170 180 190 200 210 220 230 ?80 ?85 ?90 ?95 ?100 ?105 ?115 ?110 ?20dbfs ?14dbfs ?8dbfs 12348-636 figure 33 . swept two - tone worst imd 3 vs. frequency over pass band (f = 5 mhz for two tone s, p in = 8 dbfs, 14 dbfs, and 20 dbfs) rev. 0 | page 15 of 86
AD6676 data sheet n ominal performance f or if = 250 mh z and bw = 75 mhz f if = 250 mhz, bw = 75 mhz, f ad c = 3.2 ghz, attenuator = 0 db, l ext = 19 nh, maximum pin_0dbfs setting, f data_iq = 200 msps, nominal supplies, shuffler enabled (every clock cycle), with default threshold settings, unless otherwise noted. 0.25 ?0.50 ?0.25 0 210 220 230 240 250 260 270 280 290 normalized stf response (dbfs) frequency (mhz) 12348-637 figure 34 . if pass band flatness (includes digital filter) ?150 ?151 ?152 ?153 ?154 ?155 ?156 ?157 ?158 ?159 ?160 210 220 230 240 250 260 270 280 290 nsd (dbfs/hz) input frequency (mhz) nsd (?1 dbfs signal) nsd (no signal) 12348-638 figure 35 . nsd with and without full - scale cw at 243 mhz 0 ?120 ?100 ?80 ?60 ?40 ?20 210 220 230 240 250 260 270 280 290 amplitude (dbfs/nbw) input frequency (mhz) ?1 dbfs at 288mhz nbw = 9.2khz if passband region 12348-639 figure 36 . spectral plot of if pass band region with 1 dbfs cw at 288 mhz 5 ?30 ?25 ?20 ?15 ?10 ?5 0 0 100 200 300 400 500 600 700 normalized stf response (dbfs) frequency (mhz) 12348-640 figure 37 . wideband frequency response (before digital filter) ?150 ?151 ?152 ?153 ?154 ?155 ?156 ?157 ?158 ?159 ?160 ?44 ?3 ?5 ?8 ?11 ?14 ?17 ?20 ?23 ?26 ?29 ?32 ?35 ?38 ?41 nsd (dbfs) input power (dbm) pin_0dbfs = ?2.3dbm 2.87.5mhz 2.12.5mhz 250mhz 12348-641 figure 38 . nsd vs. cw input power, cw at 243 mhz (nsd = 5 mhz, bw = 212.5 mhz, 250 mhz, and 287.5 mhz band edges) ?75.0 ?75.5 ?76.0 ?76.5 ?77.0 ?77.5 ?78.0 ?78.5 ?79.0 ?79.5 ?80.0 ?45 ?3 ?6 ?9 ?12 ?15 ?18 ?21 ?24 ?27 ?30 ?33 ?36 ?39 ?42 ibn (dbfs) input power (dbm) pin_0dbfs = ?2.3dbm 12348-642 figure 39 . ibn in the pass band region (bw = 75 mhz) vs. swept single tone input power with cw at 288 mhz rev. 0 | page 16 of 86
data sheet AD6676 0 ?120 ?100 ?80 ?60 ?40 ?20 150 170 190 210 230 250 270 290 310 330 350 worst spur (dbfs/nbw) input frequency (mhz) if pass band region worst swept spur for ?1dbfs cw at ?3.4dbm < ?88dbfs ?1dbfs at 315mhz ?79dbfs at 200mhz clock spur ?88dbfs 12348-643 figure 40 . worst spur falling in 75 mhz pass band for swept cw from 150 mhz to 300 mhz 0 ?120 ?100 ?80 ?60 ?40 ?20 210 290 280 270 260 250 240 230 220 worst spur (dbfs/nbw) input frequency (mhz) 2 tone at ?8dbfs (?10.4dbm) at 247.5mhz and 252.2mhz ?94dbfs ?102dbfs 12348-644 figure 41 . two - tone imd performance (f 1 = 2 47 .5 mhz, f 2 = 25 2 .5 mhz) worst imd3 (dbfs) input amplitude (dbfs) ?39 ?6 ?9 ?12 ?15 ?18 ?21 ?24 ?27 ?30 ?33 ?36 ?80 ?85 ?90 ?95 ?100 ?105 ?110 ?115 ?120 ?125 ?130 12348-645 figure 42 . swept two - tone worst imd3 vs . tone level (dbfs) (f 1 = 252.5 mhz, f 2 = 257.5 mhz) ?80 ?85 ?90 ?95 ?100 ?105 ?110 ?115 worst pass band spur (dbfs) input frequency (mhz) 150 170 190 210 230 250 270 290 310 330 350 ?1dbfs ?6dbfs ?12dbfs ?18dbfs 12348-646 figure 43 . swept worst pass band spur with cw swept from 150 mhz to 300 mhz for p in = 1 dbfs, 6 dbfs, 12 dbfs, and 18 dbfs 0 ?120 ?100 ?80 ?60 ?40 ?20 210 290 280 270 260 250 240 230 220 amplitude (dbfs/nbw) input frequency (mhz) ?91dbfs ?91dbfs 2 tone at ?8dbfs (?10.4dbm) at 238mhz and 262mhz 12348-647 figure 44 . two - tone imd performance (f 1 = 238 mhz, f 2 = 262 mhz) worst imd3 (dbfs) frequency (mhz) 210 220 230 240 250 260 270 280 290 300 ?80 ?85 ?90 ?95 ?100 ?105 ?110 ?20dbfs ?14dbfs ?8dbfs 12348-648 figure 45 . swept two - tone worst imd3 vs. frequency over pass band (f = 5 mhz for two tone s, p in =8 dbfs, 14 dbfs, and 20 dbfs ) rev. 0 | page 17 of 86
AD6676 data sheet n ominal p erformance for if = 350 mhz and bw = 160 mhz f if = 350 mhz, bw = 160 mhz , f ad c = 3.2 ghz, attenuator = 0 db, l ext = 10 nh, maximum pin_0dbfs setting, f data_iq = 266.7 msps, shuffler enabled (every clock cycle), with default threshold settings, unless otherwise noted. 1.00 0.75 0.50 0.25 ?0.50 ?0.25 0 270 290 310 330 350 370 390 410 430 normalized stf response (dbfs) frequency (mhz) 12348-649 figure 46 . if pass band fla tness (includes digital filter) ?140 ?142 ?144 ?146 ?148 ?150 ?152 ?154 ?156 270 290 310 330 350 370 390 410 430 nsd (dbfs) input frequency (mhz) nsd (?1 dbfs signal) nsd (no signal) 12348-650 figure 47 . nsd with and without full - scale cw at 355 mhz 0 ?120 ?100 ?80 ?60 ?40 ?20 260 280 300 320 340 360 380 400 440 420 amplitude (dbfs/nbw) input frequency (mhz) ?1 dbfs at 431mhz nbw = 12.2khz if pass band region 12348-651 figure 48 . spectral plot of if pass band region w ith 1 dbfs cw at 431 mhz 5 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 0 1000 900 800 700 600 500 400 300 200 100 normalized stf response (dbfs) frequency (mhz) 12348-652 figure 49 . wideband frequency response (before digital filter) ?140 ?142 ?144 ?146 ?148 ?150 ?152 ?154 ?156 ?44 ?3 ?5 ?8 ?11 ?14 ?17 ?20 ?23 ?26 ?29 ?32 ?35 ?38 ?41 nsd (dbfs) input power (dbm) pin_0dbfs = ?2.3dbm 300mhz 2400mhz 350mhz 12348-653 figure 50 . nsd vs. cw input power, cw at 355 mhz (nsd = 5 mhz, bw = 310 mhz, 350 mhz, and 400 mhz) ?60 ?61 ?62 ?63 ?64 ?65 ?66 ?67 ?68 ?69 ?70 ?45 ?3 ?6 ?9 ?12 ?15 ?18 ?21 ?24 ?27 ?30 ?33 ?36 ?39 ?42 ibn (dbfs) input power (dbm) pin_0dbfs = ?2.3dbm 12348-654 f igure 51 . ibn in if pass band region (bw = 160 mhz) vs. swept single tone input power with cw at 431 mhz rev. 0 | page 18 of 86
data sheet AD6676 0 ?120 ?100 ?80 ?60 ?40 ?20 220 480 460 440 420 400 380 360 340 320 300 280 260 240 worst spur (dbfs/nbw) input frequency (mhz) if pass band region worst swept spur for ?1dbfs cw at ?3.3dbm ?1dbfs at 372mhz ?77dbfs at 267mhz clock spur ?83dbfs image spur nbw = 12.2khz 12348-655 figure 52 . worst spur falling in 160 mhz pass band for swept cw from 217 mhz to 484 mhz 0 ?120 ?100 ?80 ?60 ?40 ?20 270 290 310 330 350 370 390 410 430 worst spur (dbfs/nbw) input frequency (mhz) two tone at ?8dbfs (?10.4dbm) at 340mhz and 360mhz ?93dbfs ?87dbfs nbw = 12.2khz 12348-656 fi gure 53 . two - tone imd performance (f 1 = 340 mhz, f 2 = 360 mhz) worst imd3 (dbfs) input amplitude (dbfs) ?39 ?6 ?9 ?12 ?15 ?18 ?21 ?24 ?27 ?30 ?33 ?36 ?80 ?85 ?90 ?95 ?100 ?105 ?110 ?115 12348-657 figure 54 . swept two - tone worst imd 3 vs . tone level (dbfs) (f 1 = 347.5 mhz, f 2 = 352.5 mhz) ?80 ?85 ?90 ?95 ?105 ?100 worst pass band spur (dbfs) input frequency (mhz) 220 240 260 280 300 320 340 360 380 400 420 440 460 480 ?1dbfs ?6dbfs ?12dbfs ?18dbfs 12348-658 figure 55 . swept worst pass band spur with cw swept from 217 mhz to 484 mhz over p in = 1 dbfs, 6 dbfs, 12 dbfs, and 18 dbfs 0 ?120 ?100 ?80 ?60 ?40 ?20 270 290 310 330 350 370 390 410 430 worst spur (dbfs/nbw) input frequency (mhz) two tone at ?8dbfs (?10.4dbm) at 325mhz and 375mhz ?74dbfs ?87dbfs nbw = 12.2khz 12348-659 figure 56 . two - tone imd performance (f 1 = 325 mhz, f 2 = 375 mhz) worst imd3 (dbfs) frequency (mhz) 270 290 310 330 350 370 390 410 430 ?75 ?80 ?85 ?90 ?95 ?100 ?105 ?20dbfs ?14dbfs ?8dbfs 12348-660 figure 57 . swept two - tone worst imd 3 vs. frequency over pass band (f = 5 mhz for two tone s, p in =8 dbfs, 14 dbfs, and 20 dbfs) rev. 0 | page 19 of 86
AD6676 data sheet equivalent circuits 12348-017 csb, sclk or sdi 1k? vddio figure 58 . equivalent csb or sclk input circuit dc ac vin+ vin? r in = 60 v cm = 1.0v 12348-401 figure 59 . eq uivalent analog input + ? clk+ clk? nc to clk syn to band-pass - adc 50? 50? vdd1 12348-0 1 1 figure 60 . equivalent clock input circuit sysref+ vddhsi 1k? sysref? vddhsi 1k? 10k? 10k? level translator v cm = 0.55v 12348-012 figure 61 . equivalent sysref input 12348-015 1k? vddio vddio sdio or agcx i/o esd protected esd protected figure 62 . equivalent sdio or agcx input/output circuit 12348-016 resetb 1k? vddio 25k? 20k? 20k? level translator v cm = 0.85v syncinb pin control (spi) syncinb+ vddio 1k? dgnd syncinb? vddio 1k? dgnd v cm 12348-013 figure 64 . equivalent syncinb input serdoutx+ serdoutx? data+ data? x = 0, 1 x = 0, 1 vddhsi vddhsi output driver emphasis/swing control (spi) 12348-014 figure 65 . digital cml output circuit rev. 0 | page 20 of 86
data sheet AD6676 terminology noise figure (nf) nf is the degradation in snr performance (in db) of an input signal having a noise density of ?17 4 dbm/hz after it passes through a component or system. mathematically, nf = 10 log( snr in / snr out ) the noise figure of the AD6676 is determined by the equation nf = p in ?(10 log( bw )) ?(?174.0 dbm/hz) ? snr where: p in is the input power of an unmodulated carrier. bw is the noise measurement bandwidth. ?174.0 dbm/ hz is the thermal noise floor at 290 k. snr is the measured signal - to - noise ratio in db of the AD6676 . note that p in is set to a low l evel (that is, AD6676 , being a - adc, displays a uneven nsd ac ross its if pass band . both the wors t - case nsd as well as nsd at the pass band center are reported. note that nsd is calculat ed from the ibn measured over a 5 mhz bandwidth. in -b and noise (ibn) ibn is the integrated noise power measured over a user define d bandwidth relative to the full scale of the adc (dbfs) . this bandwidth is typically equal to the if pass band setting (bw) o f the ad66 76, unless otherwise noted. input second - order intercept (iip2) iip2 is a figure of merit used to quantify the second - order intermodulation distortion (imd 2 ) of a component or system. two equal amp litude unmodulated carriers at specified frequencies (f 1 and f 2 ) injected into a nonlinear system exhibiting second - order nonlinear ities produce imd components at f 1 ? f 2 and f 1 + f 2 . for the AD6676 , the two frequencies are situated at ? the if frequency (with a 2 mhz offset) at a power level corre sponding to ? 6 dbfs at the if center frequency with only the intermodulation term at f 1 + f 2 considered. iip2 is the extrapolated tone power at which the intermodulation terms and the input tones have equal amplitude. iip2 = p in ? imd2 input third - order i ntercept (iip3) iip3 is a figure of merit used to quantify the third - order intermodulation distortion (imd 3 ) of a component or system. two equal amplitude unmodulated carriers at s pecified frequencies ( f 1 and f 2 ) injected into a nonlinear system exhibiting third - order nonlinearities produce imd components at 2 f 1 ? f 2 and 2 f 2 ? f 1 . iip3 is the extrapolated tone power at which the intermodulation terms and the input tones have equal amplitude. iip3 = p in C imd3 /2 note that the third - order imd performance of an adc does not necessarily follow the 3:1 rule that is typical of rf/if linear devices. imd performance is dependent on the dual tone frequencies, signal input levels, and adc clock rate. worst in -b and spur (sfdr) worst in - band spur is the worst spur falling in the if pass band relative to the full scale of th e adc (dbfs) when a single tone with defined power level is s tepped (typically 1 mhz increments) across a user defined frequency range. note that this worst spur can often be a n image (or clock) related spur depending on the if , bw , and iq output data rate setting of the AD6676 and on the sweep range . signal transfer function (stf) stf is the frequency response of the output signal of th e adc relative to a swept single tone at its input . the stf presented for different AD6676 setup conditions in the typical performance characteristics section shows the stf over the if pass band after the digital filter to highlight pass band flatness. t he wideband stf response is measured before the digital filter to highlight the pass band res p onse of the AD6676 - adc . rev. 0 | page 21 of 86
AD6676 data sheet rev. 0 | page 22 of 86 theory of operation overview the AD6676 is a highly integrated and flexible if subsystem capable of digitizing if signals. the ability to tune the if frequency and bandwidth allows the - adc to be optimized for different applications while trading off bandwidth for dynamic range. to facilitate its evaluation and design in, a software tool that is part of the AD6676ebz development platform must be used to configure and evaluate the device. this tool saves the spi initialization and configuration sequence to a file for later use. a screenshot of the gui front panel (see figure 66) shows the different user specified application parameters that configure the AD6676 . the following discussion provides more insight into the device operation and how these application parameters affect performance. 12348-018 figure 66. screenshot of AD6676 gui software tool that facilitates device configuration and evaluation a functional block diagram of the AD6676 is shown figure 67. the focal point of the AD6676 is its continuous time, band-pass - adc that operates with a clock rate between 2.0 ghz and 3.2 ghz. an on-chip controller configures the - adc based on the user specified application parameters. the - adc provides exceptional dynamic range and pass band flatness within the desired if span while limiting out-of-band peaking to less than 0.5 db. an on-chip clock synthesizer supplies a 2.94 ghz to 3.2 ghz - adc clock. alternatively, an external clock can be supplied for lower clock rates or improved phase noise performance. on-chip digital signal processing blocks include a quadrature digital downconverter (qddc) followed by selectable decimation filters supporting de cimation factors of 12, 16, 24, or 32. the qddc performs a complex shift of the desired if pass band such that it is centered about dc, that is, zero if. cascaded decimation filters remove the inherent out-of-band noise of the adc along with any other out-of-band signal content such that the 16-bit complex iq data is reduced to a more manageable data rate for transfer to the host via a single or dual lane jesd204b interface supporting up to 5.333 gbps lane rates. the AD6676 also includes features for agc support and/or level- planning optimization. agc support includes the ability to monitor peak power at the - adc output or rms power after the first internal decimation stage. the host can initiate fast agc action by configuring various flags whose status are made available on the agc4 to agc1 pins. flags can be set with programmable thresholds indicating whether the signal level is above or below a defined level. a 27 db attenuator with a step size of 1 db is available for if agc control or level planning optimization during initial system calibration. alternatively, the nominal 0 dbfs full-scale input power level (pin_0dbfs) of ?2 dbm can be reduced by up to 12 db thus further reducing the rf/if gain requirements. the spi programs numerous parameters of the AD6676 , allowing the device to be optimized for a variety of applications. l? l+ resetb vddio a gc4, agc3 agc2, agc1 vdd2nv vssa vdd2 vddd vssd spi csb sclk sdio sdo serdout0+ serdout0? serdout1+ serdout1? vddhsi syncinb sysref agc support clock generation ?2.0v reg jesd204b serializer tx outputs mx m = 12, 16, 24, 32 i q qddc + nco i q band-pass - ? adc vin? vin+ 27db attenuator (1db steps) clock synthesizer jesd204b subclass 1 control clk+ clk? vddc vddq AD6676 12348-400 vddl vdd1 vss2out vss2in figure 67. functional block diagram
data sheet AD6676 rin vin idac3 idac1 c array l ext reson1 reson2 reson3 a v idac1 fs adjust c3 g31 idac4 c4 g43 idac5 c5 g54 idac6 c6 g65 ?g34 ?g56 g53 17-level flash adc 17 5 17 optional shuffler encoder dout 12348-020 figure 68 . simplified single - ended representation of the band - pass - adc modulator band - pass - adc architecture figure 68 shows a simplified single - ended representation of the AD6676 band - pass - adc. it is a sixth - order modulator consisting of three cascaded second - order continuous - time resonators with feedback dacs and a n oversampling quantizer. the first resonator (reson1) is based on a lc tank with its resonant frequency tuned via c array to the if center while the second and third resonators (reson2 and reson3) are active rc - based with their resonant frequencies tuned to frequencies offset symmetrically about the if. these resonant frequencies correspond to the z ero locations of the - adc quantization noise and are set according to the user defined if frequency and bandwidth. a 17 - level flash adc oversample s the analog output of reson3 with t he digital output of the flash adc feeding back to each of the resonat ors via current mode dacs (idacx). note that because the adc thermometer code output can range from ?8 to +8, it is represented by five bits that are passed to the AD6676 d igital path. the idac1 full - scale current setting (idac1 fs ) sets the maximum full - scale input power level (pin_0dbfs). the full - scale settings of the other idacs set the pole location of the modulator to achieve a flat pass band response. lastly, a programmable shuffler follows the flash adc to improve the linearity performance of the AD6676 under la rge signal conditions. the tunable nature of the - a dc is a result of the full - scale current of the feedback dacs, as well as the conductance s (g) and capacit ances (c) associated with each resonator. the value of these programmable components are calcul ated from the user specified application parameters listed in table 7 . the impact of each of these parameters on the performance of the AD6676 is described in subsequent sections. table 7 . list of user specified application parameters that determine the - adc internal settings application parameter description spi register(s) f if if center frequency in mhz 0x102, 0x103 bw if pass band bandwidth in mhz 0x104, 0x105 f ad c - adc clock rate in mhz 0x100, 0x101 l ext external inductor val ue in nh 0x106 mrgn margin offset to set resonator frequency in mhz 0x107 to 0x109 idac1 fs full - scale current of idac1 that sets pin_0dbfs level 0x10a the on - chip controller is used only during device initialization and performs the following tasks: ? pow er - up negative regulator (used by idacs) ? calibrate reson1 and 17 - level flash adc ? tune - adc based on user input parameters ? set up pll used by jesd204b phy after device initialization, the on - chip controller is disabled ; it is not used during normal device operation. signal and noise transfer functions the frequency domain response o f a - adc is defined by its signal and noise transfer functions (stf and ntf). figure 69 shows a simplified feedback model of a - modulator with the adc quantization error modeled as an additive noise source (e) after the loop filter (h). the stf is the frequency response of the output signal (v) relative to a swept single tone at its input (u) while the ntf is the frequency response of the adc quantization noise (that is, v/e) that undergoes noise shaping due to of the loop fi lter of the adc . note that the adc and dacs within the feedback loop operate at a much higher clock rate than a traditional open - loop adc in which only the nyquist criterion must be satisfied ( f ad c = 2 bw). the oversampling ratio (osr) is a key paramete r of any - adc and is defined as follows: osr = f ad c /(2 bw ) (1) rev. 0 | page 23 of 86
AD6676 data sheet dac adc loop filter h(s) + ? u u v dac h(z) + ? v adc e u(z) v(z) = h(z) 1 + h(z) stf e(z) + 1 1 + h(z) ntf 12348-021 figure 69 . simplified model of a - adc showing origins of stf and ntf in the case of the AD6676 , the loop filter consists of three cascaded resonators to implement a sixth - order band - pass response, thus allowing the oversampling ratio of the AD6676 to be kept to moderate levels (10) such that useable bandwidths of up to 160 mhz can be realized. the loop filter utilizes a feedback architecture so that the stf has minimal out - of - band gain peaking while the ntf suppresses the in - band quantization nois e. figure 70 shows an example of the stf and the shaped noise of the - adc when it is configured for bw = 80 mhz, f if = 300 mhz, and f ad c = 3.2 ghz. note that the nsd near f if is much lower than the nsd elsewhere and that the st f is quite broadband. 0 ?120 ?100 ?80 ?60 ?40 ?20 0 200 400 600 800 1000 1200 1400 1600 noise (dbfs/nbw) frequency (mhz) stf nsd = ?161.5dbfs/hz ntf shaped noise nbw = 146.5khz 12348-022 figure 70 . stf and ntf shaped noise of the - adc (f if = 300 mhz, bw = 80 mhz, f ad c = 3.2 ghz, l ext = 19 nh) figure 71 focuses on the if pass band region to compar e the measured vs. ideal shaped noise with the theoretical nsd curve accounting only for the ideal adc quantization effect. the resonator zero locations are highlighted on the theoretical trace and are recognizable in the measured response. note that the r egion with the lowest nsd performance or the deepest notch is always centered about the f if setting. this is because the gain of reson1 peaks at f if and the noise from stages which follow reson1 is input referred by dividing by the gain of reson1. ?60 ?130 ?120 ?130 ?140 ?150 ?160 ?170 ?180 ?120 ?110 ?100 ?90 ?80 ?70 100 150 200 250 300 350 400 450 500 noise (dbfs/nbw) (dbfs/hz) frequency (mhz) reson2 reson1 reson3 theoretical nsd from adc quantization observed nsd nbw = 146.5khz 12348-023 figur e 71 . measured vs. ideal ntf (f if = 300 mhz, bw = 80 mhz, f ad c = 3.2 ghz, l ext = 19 nh) unlike conventional adcs, the nsd of a - adc is not flat due to its frequency dependent loop filter, h(s), which shap es the quantization noi se as well as various other noise sources. because the - adc is highly programmable, its nsd can be optimized for the user specified application parameter settings. in general, the nsd performance varies based on the application parameter settings in the following ways: ? operating with a high oversampling ratio (osr > 20) results in the lowest and flattest nsd performance. this is because the resonant frequencies (or zero locations) associated with reson1, reson2 , and reson3 are close together when the ov ersampling ratio is high thereby reducing the quantization noise to the point where thermal noise from the first stage idac1 dominates. ? operating at reduced oversampling ratio ( oversampling ratio < 20) causes the quantization noise contribution to become m ore significant , causing humps to appear in the nsd. bumpiness in the nsd occurs because the resonant frequencies associated reson2 and reson3 are further offset from reson1 to accommodate the increase in bw ; therefore , resulting in less overall loop gain to suppress this increasingly dominant noise source. the effect of different oversampling ratio s on the nsd is shown in figure 72. ? operating at a lower f if while keeping the same oversampling ratio results in degraded nsd perform ance at the pass band edges, as shown in figure 73. rev. 0 | page 24 of 86
data sheet AD6676 ?130 ?160 ?155 ?150 ?145 ?140 ?135 200 220 240 260 280 300 320 360 400 340 380 noise (dbfs/hz) frequency (mhz) osr = 10 (bw = 160mhz) osr = 20 (bw = 80mhz) osr = 40 (bw = 40mhz) osr = 80 (bw = 20mhz) 12348-024 figure 72 . nsd vs. oversampling ratio ( f if = 300 mhz, f ad c = 3.2 ghz, l ext = 19 nh) ?140 ?160 ?158 ?156 ?154 ?152 ?150 ?148 ?146 ?144 ?142 ?100 ?80 ?60 ?40 ?20 0 20 60 100 40 80 noise (dbfs/hz) normalized zero if frequency (mhz) if = 100mhz with l ext = 100nh if = 200mhz with l ext = 43nh if = 300mhz with l ext = 19nh 12348-025 figure 73 . nsd at pass band edge impro vement as f if is increased from 100 mhz to 300 mhz with fixed oversampling ratio = 16 (bw = 100 mhz, f ad c = 3.2 ghz) the impact of a uneven nsd profile on a particular application depends on the bandwidth and modulation characteristics of the if signal be ing digitized and demodulated. for example, a multimode software defined radio containing narrow - band carriers situated anywhere across the pass band must consider the nsd performance at the highest levels across the pass band because this represents the w orst - case nsd when calculating the in - band noise for a narrow - band signal in this region. conversely, a single wideband qam signal falling at the center of the if pass band benefits from excellent in - band noise performance because the nsd remains the lowes t in this region. note that the AD6676 specified nf is measured in the region where its nsd is highest. stf and ntf repeatability af ter the application parameters have been determined, the stf and ntf characteristics of the AD6676 remain repeatable and stable over t emperature and among devices. the on - chip calibration performed during the power - up initialization phase reduces the device - to - device variation that may otherwise exist due to tolerances associated with the device process or the external inductor, l ext . it is worth noting that that the small variation in stf and ntf that does exist is likely to be less than traditional receiver solutions employing low oversampling adcs with aggressive high order lc antialiasing filters. l and c component tolerances as wel l as variation in active device source and load impedances must be considered in the monte carlo analysis. the following application parameters were used to demonstrate stf and ntf repeatability: f clk = 3.2 ghz, f if = 25 0 mhz, bw = 75 mhz, l ext = 19 n h, ida c1 fs = 4 ma, mrgn = default. figure 74 and figure 75 demonstrate the repeatability and temperature stability of the stf and ntf responses of single devices for five consecutive power - up initialization ope rations in which the device is calibrated at 25c and then allowed to drift to ?40c and +85c. 0.2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 200 210 220 230 240 250 260 280 300 270 290 normalized stf (dbfs) frequency (mhz) 12348-700 t a = ?40c t a = +25c t a = +85c figure 74 . stf variation over temperature for a single device for five consecutive power - up initialization operations ?146 ?148 ?150 ?152 ?154 ?156 ?158 ?160 200 210 220 230 240 250 260 280 300 270 290 nsd (dbfs) frequency (mhz) 12348-701 t a = ?40c t a = +25c t a = +85c figure 75 . ntf variation over temperature for a single device for five consecutive power - up initialization operations rev. 0 | page 25 of 86
AD6676 data sheet - adc overload and recovery the - adc is a sixth - order modulator employing negative feedback to reduce the noise c ontribution of its internal quantizer. like any adc, the quantizer is driven into overload under large signal conditions, causing its output to be a poor representation of its input. however, unlike traditional adcs that operate in open - loop, a - adc can be driven into overload with signals slightly below its 0 dbfs full - scale input level and the feedback loop can become unstable and may not return to normal operation when the overload condition is removed. a typical unstable - adc produces a digital ou tput that varies between plus or minus full scale . the AD6676 employs several techniques to solve these problems. first, to m ake the n o overload range with continuous wave tones approach levels near 0 dbfs, the AD6676 uses a 5 - bit quantizer. the AD6676 is specified to remain unconditionally stable for continuous wave levels below ?2 dbfs over its full operation range, with a typical overload level o f ?0.5 dbfs. in practice, the large signal waveform characteristics that determine the occurrence and duration of its peaks affect the overload threshold. a continuous wave tone is close to the worst - case scenario for overload because the peak levels have the highest probability of occurrence. alternatively, a signal that ha s a much higher crest factor and a more gaussian - like histogram is less likely to cause overload due to the short duration of its peak excursions. for this reason, for systems employing agc, consider the waveform characteristics when setting the agc threshold. second, to ensure that the adc does not become stuck in a self sustaining overload condition, the AD6676 includes the means to detect overload, reset the - adc, and quickly return it to normal operation. an overload condition is declared if more than five out of eight samples from the quantizer are equal to a po sitive or negative ful l- scale value. after overload is detected, the internal nodes within the - adc are reset to their zero state and the attenuation setting is temporarily increased by 6 db. the adc reset is removed after 16 f ad c clock cycles and over the next 48 f ad c clock cycles , the attenuation is returned to its original value. if the input signal is such that an overload occurs again, this process repeats until the signal falls within the no overload range of the - adc. although the - adc produ ces good data within 64 f ad c clock cycles of the signal falling within the no overload range, the bad data associated with an overload event must be flushed out of the decimation filters before the output of the AD6676 is completely clean of any memory effects. figure 76, figure 77, figure 78 , and figure 79 show the measured overload recovery response for each of the decimation fi lter modes (dec_mode) when driven by a periodic pulsed cw waveform of 10 ns duration and 2% duty cycle. the narrow pulse region of the waveform was set to be o nly 1 db higher than the other region with its peak power adjusted slightly above the overload threshold level resulting in an occasional overload event. each plot compares the envelope response between a pulse that results in an overload event to a pulse where the - adc remains stable and includes a zoom in region showing settling time to within 1% following the large scale settling plot . because t he phase response recovers two to three samples before the envelope response , the phase response is not show n. note the following: ? the AD6676 was configured for f if = 300 mhz, bw = 100 mhz, and f ad c = 3.2 ghz. ? the absolute settling response f or any decimation factor scales with f data_iq . for example, the settling time shown in figure 77 is an additional seven samples at f data_iq = 200 msps, thus the absolute settling time is 35 ns (7 1/200 msps). ? selecting a decima tion factor of 12 or 16 improves the absolute settling time because it reduces the additive delay caused by the last stage decimation filter. 1.0 0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 95 97 99 101 103 105 107 109 111 113 115 normalized iq magnitude response samples zoom-in of large scale settling response for 1% settling large scale settling no overload/ recovery overload/ recovery 7 samples @ 266.7msps 12348-030 figure 76 . comparison of normalized iq magnitude response for decimate by 12 case w hen a pulsed cw waveform (10 ns width) is just below and above peak power level, resulting in adc overload 1.1 1.2 1.0 0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05 1.06 1.07 1.08 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0 2 4 6 8 10 12 14 16 18 20 normalized iq magnitude response samples zoom-in of large scale settling response for 1% settling large scale settling no overload/ recovery overload/ recovery 7 samples @ 200msps 12348-031 figure 77 . comparison of normalized iq magnitude response for decimate by 16 case w hen a pulsed cw waveform (10 ns width) is j ust below and above peak power level , resulting in adc overload rev. 0 | page 26 of 86
data sheet AD6676 1.0 0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05 1.06 1.07 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0 2 4 6 10 8 12 14 16 18 20 normalized iq magnitude response samples zoom-in of large scale settling response for 1% settling large scale settling no overload/ recovery overload/ recovery 6 samples @ 266.7msps 12348-032 figure 78 . comparison of normalized iq magnitude response for decimate by 24 case w hen a pulsed cw waveform (10 ns width) is just below and above peak power level, r esulting in adc overload 1.1 1.2 1.0 0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05 1.06 1.07 1.08 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0 2 4 6 8 10 12 14 16 18 20 normalized iq magnitude response samples zoom-in of large scale settling response for 1% settling large scale settling no overload/ recovery overload/ recovery 5 samples @ 100msps 12348-033 figure 79 . comparison of normalized iq magnitude response for decimate by 32 case w hen a pulsed cw waveform (10 ns width) is just below and above peak power level, resulting in adc overload - adc configuration consid erations maximum input power (pin_0dbfs and idac1 fs ) the AD6676 maximum full - scale input power (pin_0dbfs) for a sinusoidal input signal is dependent on the idac1 peak full - scale output current (idac1 fs ) and the r in of the attenuator (that is, 6 0 ?) as shown in the equation below. pin_0dbfs = 10 log10(1/2 r in idac1 fs 2 ) (2) the derivation of this equation becomes apparent when considering the AD6676 input stage consisting of reson1, idac1, and r in , as shown in f igure 68. r in is the input resistance of the attenuator. the casc o de transistor associated with idac 1 and r in establishes a low impedance node serving as a current mode summing junction whereby the input signal (equal to vin / r in ) is compared to the feedb ack signal from idac1. note that the feedback loop of the - modulator attempts to generate an equal but opposite feedback current to cancel the signal current appearing at this summing junction. ultimately, the maximum feedback signal current that can be generated by idac1 is limited by its full - scale setting, idac1 fs , thus setting the 0 dbfs level on which feedback can no longer cancel any further increase in input signal level (or power). for example, the AD6676 nominal setting for idac1 fs at 4 ma equates to a pin_0dbfs of ?3 dbm, resulting in a d ifferential voltage swing of 24 0 mv peak. equation 2 assumes that the attenuator setting is 0 db. any setting beyond 0 db inc reases the effective pin_0dbfs measure d at the input of the attenuator by a n amount equal to the attenuator setting. in practice, the actual measured pin_0dbfs may vary a few tenths of a decibel for different application parameter settings due to some amount of pass band tilt. for this reason, pin_0dbfs is defined at the if cent er. l ext selection the range of permissible values for l ext depends on the following a pplication parameters: f if , f ad c , and idac1 fs . figure 80 shows the upper and lower settings ( l max and l min ) when idac1 fs is set to its default settings of 4 ma. note that the l max limit is set by the largest voltage swing across the lc tank and the l min limit is set by the maximum tuning capacitance available from an internal capacitor array. 200 5 10 20 15 100 0 100 200 300 400 500 50 150 250 350 450 l ext (nh) f if (mhz) absolute maximum maximum for f adc = 3.2ghz maximum for f adc = 2.6ghz maximum for f adc = 2.0ghz minimum 12348-034 figure 80 . maximum extern al inductor value as a function of if frequency and clock rate for idac1 fs = 4 ma note the following points when selecting l ext : ? larger values of l ext result in larger voltage swings across the lc tank. selecting a value that is approximately 55 % to 80% of the l max value can be considered with a lower value , typically resulting in improved imd performance due to reduced voltage swing across the inductor . conversely, a higher value may lead to a slight improvement in noise performance (mostly near the if cen ter ) , but at the expense of imd performance . ? inductor accuracy of 10% is sufficient because it falls well within the calibration range of the AD6676 during its initialization phase on power - up. rev. 0 | page 27 of 8 6
AD6676 data sheet rev. 0 | page 28 of 86 ? surface mount inductors can be either wire-wound or multilayer. the lower cost multilayer inductors typically have quality factors below 20 that may have a slight impact on the AD6676 nsd performance. compare performance between the two inductor types before making a decision to select a lower cost multilayer type. ? because the voltage swing across the lc tank scales proportionally with idac1 fs , which sets pin_0dbfs, a reduction in idac1 fs allows an inversely proportional increase of l ext to maintain a similar voltage swing. note that the minimum tuning capacitance from the internal capacitor array along with any parasitic pcb capacitance sets largest the l ext as defined in equation 3. l max_tune = ((2 f if ) 2 7.1 pf) ?1 (3) the minimum capacitance contribution of the array can be up to 6.6 pf due to 20 process variation. an additional 0.5 pf of pcb parasitic capacitance is also included, thus a value of 7.1 pf is used. tie the two external inductors, l ext , to the vdd2 supply via a 10 resistor that includes a 0.1 f decoupling capacitor, as shown in figure 93. the following example highlights how l ext can be determined with the following application parameters: f if = 150 mhz, f adc = 3.0 ghz and idac1 fs = 4 ma. referring to figure 80, the l max and l min range is from 20 nh to 70 nh. a value of 43 nh represents 61% of l max and thus is suitable. note that if the idac1 fs is reduced to 2 ma, this value can be increased to 86 nh because this value is below the absolute maximum. reduced pin_0dbfs operation via scaling idac1 fs the pin_0dbfs can be reduced by up to 12 db because idac1 fs is adjustable over a 4 ma to 1 ma span as defined by equation 4. idac1 fs = 4 ma ( idac1_fs /64) (4) where idac1_fs is the decimal equivalent of the value in register 0x10a. the l ext value can be increased proportionally to any reduction in idac1 fs to maintain similar voltage swings across the lc tank. the nsd and imd performance are shown in figure 81 and figure 82 for idac1 fs settings of 4.0 ma, 2.0 ma, and 1.0 ma. figure 83 shows the stf response for each of these cases. note the following observations from this example: ? with an if of 300 mhz, the absolute maximum inductor is 39 nh; therefore, this inductor value is selected for both idac1 fs = 2.0 ma and 1.0 ma. ? reducing idac1 fs from 4.0 ma to 2.0 ma and doubling l ext lowers the pin_0dbfs by 6 db but increases the average in-band noise, ibn, by only 1.8 db. the noise figure of the adc therefore improves by 4.2 db. ? reducing idac1 fs from 2.0 ma to 1.0 ma lowers the adc full scale by a further 6 db and increases the average in- band noise by only 4.6 db. in this case, the noise figure improvement is a modest 1.4 db. ? the swept imd performance shows a degradation at reduced idac1 fs settings. ? the stf response remains largely unaffected by reduced idac1 fs settings. ? 145 ?160 ?155 ?150 250 260 270 280 290 300 310 320 330 340 350 nsd (dbfs/hz) input frequency (mhz) idac1 fs = 1ma, l ext = 39nh (ibn = ?67.9dbfs) idac1 fs = 2ma, l ext = 39nh (ibn = ?72.5dbfs) idac1 fs = 4ma, l ext = 19nh (ibn = ?74.3dbfs) 12348-035 figure 81. nsd vs. idac1 fs setting with decimate by 16, i/q output (if = 300 mhz, bw = 100 mhz, f adc = 3.2 ghz) ? 80 ?98 ?92 ?86 ?82 ?94 ?88 ?84 ?96 ?90 250 260 270 280 290 300 310 320 330 340 350 worst imd spur (dbfs) frequency (mhz) idac1 fs = 4ma (19nh) idac1 fs = 2ma (39nh) idac1 fs = 1ma (39nh) 12348-036 figure 82. swept dual-tone imd vs. idac1 fs setting with decimate by 16, i/q output, dual tones set to ?8 dbfs (if = 300 mhz, bw = 100 mhz, f adc = 3.2 ghz) 0.5 ?0.5 ?0.1 0.2 0.4 ?0.2 0.1 0.3 ?0.3 ?0.4 0 250 260 270 280 290 300 310 320 330 340 350 normalized stf response (dbfs) frequency (mhz) idac1 fs = 4ma (19nh) idac1 fs = 2ma (39nh) idac1 fs = 1ma (39nh) 12348-037 figure 83. stf vs. idac1 fs setting with decimate by 16, i/q output, dual tones set to ?8 dbfs (if = 300 mhz, bw = 100 mhz, f adc = 3.2 ghz)
data sheet AD6676 rev. 0 | page 29 of 86 some applications may benefit from a reduced idac1 fs setting because a reduction in the pin_0dbfs levels results in a decibel per decibel reduction in the gain and linearity (p1db, iip3) requirements of the front-end driver. this enables a lower power rf line-up with the possibility of 3.3 v operations. alternatively, it can allow a greater if agc operation range from the AD6676 when the previous stages output (p1db) level is set by its power supply setting. carefully evaluate the trade- off in the ac performance of the AD6676 when deciding to operate at reduced idac1 fs settings. using the mrgn parameter to optimize ntf the mrgn application parameters provide an additional degree of freedom when trying to optimize the ntf for a particular application. this feature is particularly useful when the AD6676 operates with a low oversampling ratio where the quantization noise contribution begins to limit the nsd performance. in such cases, the default mrgn settings may not be adequate, resulting in regions of the pass band (typically at the edges) where the worst-case nsd is higher than in other regions. for these cases, the ntf can be optimized by adjusting the - adc resonator frequencies in such a way that that result in a more optimally distributed nsd over the entire pass band. the mrgn_l, mrgn_u, and mrgn_if parameters are located in register 0x107 through register 0x109. mrgn_l and mrgn_u specify the number of megahertz by which the lower and upper edges of the target pass band are extended, whereas mrgn_if specifies the resonance frequency offset of reson1 from the center of the target pass band. the maximum setting in these registers must be in the range of 10 mhz to 20 mhz because higher offset settings can adversely affect the stf. the mrgn parameter is represented as an array equal to [mrgn_l, mrgn_u, mrgn_if]. the following example using a low oversampling ratio of 10 highlights the effects of the mrgn parameters on the ntf and stf. in this example, the goal is to optimize the worst-case nsd performance across a 160 mhz pass band region with f adc = 3.2 ghz and if = 300 mhz while trying to preserve a flat stf. figure 84 shows the corresponding ntf performance for different mrgn settings, and table 8 lists the resonant frequencies of reson1, reson3, and reson3 that pertain to these settings. note that the default setting of [5 5 0] results in the upper half of the pass band having the worst nsd (?141 dbfs/hz at 380 mhz). symmetrical mrgn settings of [10 10 0] and [15 15 0] are shown to highlight how the ntf varies as only the resonant frequencies of reson2 and reson3 are increasingly offset symmetrically about the if center of 300 mhz. to improve on the default setting of [5 5 0], an asymmetrical setting of [8 16 2] that is weighted towards the upper half of the pass band region was found to achieve a more distributed worst-case nsd of ?145 dbfs/hz. table 8. resonator frequencies vs. mrgn settings (f adc = 3.2 ghz, f if = 300 mhz, bw = 160 mhz) mrgn_l mrgn_u mrgn_if reson2 (mhz) reson1 (mhz) reson3 (mhz) 5 5 0 233 298 365 10 10 0 229 299 370 15 15 0 227 298 373 8 16 2 230 306 374 ? 140 ?155 ?150 ?145 220 240 260 280 300 320 340 360 380 nsd (dbfs/hz) input frequency (mhz) mrgn = [5 5 0] mrgn = [15 15 0] mrgn = [10 10 0] mrgn = [8 16 2] 12348-038 figure 84. nsd performance for mrgn settings shown in table 8 maintaining a flat stf across the pass band is also desirable when modifying the mrgn settin gs. figure 84 shows how each of the different mrgn settings affects the stf. note that the asymmetrical mrgn setting of [8 16 2] results in an stf that is slightly skewed above if center but still maintains 0.5 db flatness. 0.25 ?1.25 ?0.75 ?0.25 0 ?1.00 ?0.50 220 240 260 280 300 320 340 360 380 normalized stf response (dbfs) frequency (mhz) mrgn = [8 16 2] mrgn = [10 10 2] mrgn = [15 15 2] mrgn = [5 5 0] 12348-039 figure 85. stf for four different mrgn settings whereas the previous example represents an extreme case, other cases having higher oversampling ratio can also potentially benefit from optimization. after the values of f clk , if, and bw have been determined for a particular application, it may be advantageous to explore whether a different mrgn setting yields any improvement. it is important to note that this sort of optimization is based on an iterative trial and error method. however, after the mrgn setting has been determined, both the stf and ntf remain repeatable.
AD6676 data sheet - adc adaptive shuffler the AD6676 includes a pro grammable adaptive shuffler that improve s the sfdr and imd performance of the - adc under large signal conditions. as shown in figure 68 , the adaptive shuffler randomizes the selection of the unit elements used b y the feedback dacs to reconstruct the output signal of the quantizer. both static and dynamic mismatch errors associated with the quantizer and feedback dacs are dithered such that the spurious contribution is spread across a wider frequency span. figure 86 compares the improved imd performance for a two tone excitation when the shuffler is enabled and disabled. 0 ?120 ?100 ?80 ?60 ?40 ?20 0 ?120 ?100 ?80 ?60 ?40 ?20 140 150 160 170 180 190 200 210 220 amplitude (dbfs) amplitude (dbfs) frequency (mhz) adaptive shuffling disabled adaptive shuffling enabled shuffle every one adc clock cycle (0x342 = 0xf5, 0x343 = 0xff) 12348-040 figure 86 . imd performance when shuffler is disabled vs. enabled for two cw tones at ?8 dbfs, ( f if = 180 mhz, bw = 80 mhz, f ad c = 3.2 ghz, l ext = 43 nh) although the shuffler improves the sfdr and imd performance , it does so at the expense of the in - band nsd performance. for this reason, both the degree of shuffling as well as the enabling threshold relative to the quantizer output code is user programma - bl e, allowing optimization for a target application. the shuffling rate is variable from 1 to 4 adc clock cycles (1/ f ad c ). the shuffler remains enabled for a fixed amount of cl ock cycles from the instant that the input signal falls below this threshold and remains below it. the enabling threshold is relative to the quantizer code and represents the peak absolute value that triggers the shuffler. the quantizer can produce an out put code ranging from ?8 to +8, therefore the threshold can assume a value between 0 to 8. the 4 - bit value is set via register 0x342 or register 0x343. a hexadecimal value of 0x0 sets the shuffler to always enabled whereas a value of 0xf effectively disabl es the shuffler. the 4 - bit fields in register 0x342 and register 0x343 set the thresh - old value based on the shuffling rate selected . set only the 4 - bit field pertaining to the selected shuffling rate while the remainin g nonapplicable 4 - bit fields set to 0 x f. disable the shuffler by setting all the 4 - bit fields to 0xf, the highest threshold setting. table 9 shows the spi register settings for the various shuffling modes w hen the threshold is set to its default setting of 5. other threshold values ranging from 3 to 8 are also possible. table 10 shows the input power level that triggers the shuffler for different threshold value settings when driven by a continuous wave tone. table 9 . default spi register settings for adaptive shuffling shuffling rate register 0x342 register 0x343 f ad c 0xf5 0xff f ad c /2 0x5f 0xff f ad c /3 0xff 0xf5 f ad c /4 0xff 0x5f disable s huffler 0xff 0xff table 10 . threshold setting val ue s that trigger the shuffler for a c ontinuous wave tone p in (dbfs) threshold setting ?3 8 ?5 7 ?7 6 ?10 5 ?14 4 ?20 3 when enabled, the shuffler can introduce colored noise into the pass band spectrum. this additional noise is a result of the inc reased switching activity within the - adc core along with the pseudorandom element selection process , thus resulting in signal level dependent colored noise at frequency offsets related to the shuffling rate. figure 87 highligh ts the effect of the colored noise between shuffle every four clock cycles vs. one cycle with and without a large signal continuous wave tone present and the shuffling threshold set to 0. typically, the shuffling threshold is set in the range of 4 to 6. t his example serves to highlight the colored noise effects of shuffling. selecting a higher threshold setting is preferable when trying to preserve the nsd performance. for this reason, the AD6676 default threshold setting is 5 with the shuffle every clock cycle option. the four - cycle option introduces visible noise humps with a ?1 dbfs signal level. this colored noise is at an offset of f clk /128, resulting from the pseudorandom element selection process. other shuffling options also introduce colored noise but at a greater frequency offset that are related to the shuffling rate factor (sr f ) as described by the following equation: frequenc y offset = f clk /( 32 sr f ) (5) the effect of this colored noise is worthy of consideration when selecting the shuffling rate and threshold. for example, sweeping a ?1 dbfs continuous wave tone across the usable if pass band region while monitoring the nsd characteristics is helpful to identify what shuffling rate may have the least impact on the nsd performance. rev. 0 | page 30 of 86
data sheet AD6676 rev. 0 | page 31 of 86 ? 140 ?142 ?144 ?146 ?148 ?150 ?152 ?154 ?156 ?158 ?160 140 150 160 170 180 190 200 210 220 noise (dbfs/hz) input frequency (mhz) shuffle every 1 adc cycle ibn = ?75.5dbfs shuffle every 4 adc cycles ibn = ?76.3dbfs shuffle disabled ibn = ?77.4dbfs 12348-094 figure 87. nsd performance of the various shuffling settings with no signal; threshold set to 0 (shuffler is always enabled); f if = 180 mhz, bw = 80 mhz, f adc = 3.2 ghz, l ext = 43 nh ? 140 ?142 ?144 ?146 ?148 ?150 ?152 ?154 ?156 ?158 ?160 140 150 160 170 180 190 200 210 220 noise (dbfs/hz) input frequency (mhz) shuffle every 1 adc cycle ibn = ?73.6dbfs shuffle every 4 adc cycles ibn = ?74.0dbfs shuffle disabled ibn = ?74.6dbfs 12348-041 figure 88. nsd performance of the various shuffling settings with a ?1 dbfs signal; threshold set to 0 (shuffler is always enabled); f if = 180 mhz, bw = 80 mhz, f adc = 3.2 ghz, l ext = 43 nh the degradation in nsd performance is also dependent on the input signals amplitude; thus, it is important to select a shuffling rate and threshold setting that result in an optimum trade-off between large signal linearity performance and low signal level in-band noise performance. figure 89 shows how the in-band noise (dbfs) degrades at increasing signal levels for the same settings used in figure 87. in this example, a continuous wave tone is placed just above the pass band with its power swept from ?40 dbfs to ?1 dbfs. at low signal levels (less than ?20 dbfs), the degradation in in-band noise performance is dependent on the shuffling rate. at higher signal levels (greater than?20 dbfs), the degradation is a result of increased colored noise falling in the pass band. selecting a shuffle rate of every two adc cycles with a threshold in the range of 4 or 5 is a good compromise, as shown in figure 90. ? 74 ?75 ?76 ?77 ?78 ?79 ?800 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 ibn (dbfs) input power (dbfs) shuffling every 1 adc cycle shuffling every 2 adc cycles shuffling every 4 adc cycles shuffling every 3 adc cycles shuffling disabled 12348-042 figure 89. pass band degradation in ibn (dbfs) as a continuous wave tone at 225 mhz, swept from ?40 dbfs to ?1 dbfs with di?erent shu?ing rate settings, threshold set to 0, f if = 180 mhz, bw = 80 mhz, f adc = 3.2 ghz, l ext = 43 nh ? 74 ?75 ?76 ?77 ?78 ?79 ?80 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 ibn (dbfs) input power (dbfs) shuffling disabled shuffling every 2 adc cycles threshold = 4 shuffling every 2 adc cycles threshold = 5 12348-043 figure 90. ibn vs. input power performance for threshold settings of 4 and 5 when configured for shuffle every two adc cycles after a particular shuffling configuration is selected, the effects on the - adc performance remain repeatable over time and among different devices - adc profile feature the AD6676 includes a feature that allows the - adc to store up to four different profile settings that can be recalled quickly via register 0x118 without recalibrating the - adc. calibration of each of the different profiles specified in register 0x115 occurs during the device initialization phase with each profile consisting of the following various application parameters: bw, f if , idac1 fs , and mrgn. f adc , along with the decimation filter and jesd204b settings, remains common to ensure that the jesd204b link is maintained when switching between profile settings. note that the - adc is operational with the updated profile settings within 1 s upon receipt of the spi command.
AD6676 data sheet the following example highlights how this feature is used for applications that require wide bandwidth capability but not necessarily instantaneous bandwidth. in these applications, it may be possible to divide the required if bandwidth into narrow sub bands where the - adc can provide higher dynamic range. for instance, in an application that requires 120 mhz of if bandwidth, a user may consider dividing this bandwidth into three contiguous blocks of 40 mhz, with each if being offset by 40 mhz. figure 91 shows that the worst - case nsd is limited to ?149 dbfs/hz when the AD6676 is configured for the wider ban dwidth of 120 mhz. figure 92 shows how the nsd performance is improved by 10 db when the 120 mhz bandwidth is subdivided into three 40 mhz bands. ?145 ?160 ?155 ?150 200 220 240 260 280 300 320 noise spectral density (dbfs/hz) input frequency (mhz) profile = 0 (if = 260mhz, bw = 120mhz) 12348-100 ?149dbfs/hz figure 91 . nsd performance with wideband profile ( f if = 260 mhz, bw = 120 mhz, f ad c = 3.2 ghz, l ext = 27 nh) ?145 ?160 ?155 ?150 200 220 240 260 280 300 320 noise spectral density (dbfs/hz) input frequency (mhz) profile = 1 (if = 260mhz, bw = 40mhz) profile = 2 (if = 300mhz, bw = 40mhz) profile = 0 (if = 220mhz, bw = 40mhz) 12348-101 ?159dbfs/hz figure 92 . nsd performance with narrow - band profiles ( f if = 220 mhz, 260 mhz, and 300 mhz, bw = 120 mhz, f ad c = 3.2 ghz, l ext = 27 nh) in this example, the frequency and phase settings of the digital mixer remained common among the various profiles such that it remained centered upon 260 mhz. it is also possible to provide a unique digital mixer setting for each profile if it is desirable to re - center the digital if frequency. t his feature is desirable in instances where the range of ifs cannot be supported b y the pass band response of the digital decimation filter. attenuator the AD6676 includes an on - chip differential 27 db attenuator with a resolution of 1 db. attenuator can be used to rescale the full - scale input level into the adc for system calibration or optimization purposes or to prevent possible ove rload of the - adc when used with external agc control. figure 93 shows a simplified equivalent circuit of the AD6676 input stage, which includes reson1 and idac1. the attenuator provides a nominal input resistance (r in ) of 6 0 ? to the signal source to facilitate its interface to external driver circuitry. the attenuator is configurable via register 0x181 t o register 0x183 and includes options for fast external gain control via the agc pins. 0.1f dc ac idac1 attenuator 0db to 27db = 1db reg 0x180 to 0x181 vin+ l? l+ vin? r in = 60 v cm = 1.0v c array summing junction 10? vdd2 = 2.5v l ext l ext AD6676 12348-044 figure 93 . simplified equivalent input attenuation is achieved by a programmable shunt and series resistor network that steers some designate d amount of input current away from the summing junction while keeping the nomi nal input resistance near 6 0 ? over the full attenuation span. for a 0 db setting, no shunt resistance exists ; therefore , all of the input current is fed into the summing junction. for a 6 db setting, the attenuator is configured with a 1 2 0 ? shunt resistor operating in parallel wit h two 6 0 ? series resistors such that half of the signal input current is directed into the summing junction whi le maintaining a nominal 6 0 ? input resistance. other settings function in a similar manner with resistor values modified to achieve the desired attenuation value while maintaining the nominal r in . figure 94 shows the differential s11 of the AD6676 input for different attenuator settings. rev. 0 | page 32 of 86
data sheet AD6676 ?10 ?12 ?14 ?16 ?18 ?20 ?22 ?24 ?26 ?28 ?30 0 100 200 300 400 500 600 800 1000 700 900 s11 (db) frequency (mhz) 12348-702 0db 2db 4db 6db 8db 10db 12db 14db figure 94 . differential s11 vs. frequency for different attenuator settings the accuracy of the attenuator is an important consideration in applications implementing agc or system calibration. the attenuator remains monotonic over its full operating range. figure 95 , which shows a typical devices attenuation error vs. attenuation s tate at ?40c, +25c, and +85c, demonstrates the near instrumentation level accuracy of the AD6676 attenuator. 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0 27 24 21 18 15 12 9 6 3 step size error (db) attenuator setting (db) ?40c +25c +85c 12348-046 figure 95 . typical attenuation step size error vs. setting over temperature the linearity performance of the attenuator is another consideration when determining the largest input drive levels before its nonlinearity may dominate over that of the - adc. the effective pin_0dfs level of the AD6676 is increased decibel - per - decibel by the attenuator setting. at large attenuato r settings, the peak - to - peak voltage swing seen at the vin+ and vin? pins increases as well as the current that is steered into the attenuator shunt resistance. at a certain level, the imd c ontribution from the attenuator begins to dominate over the - ad c contribution. figure 96 plots the worst third - order imd spurious vs. attenuator setting for idac1 fs of 4 ma and 2 ma with the power of the dual tones increased to maintain a constant ? 8 dbfs level measured by the - adc. the ef fective pin_0dbfs is also plotted to show the maximum continuous wave signal level into the device that results in a 0 dbfs level. note the following conditions and observations: ? the AD6676 is configured as follows: if = 180 mhz, bw = 80 mhz, and f clk = 3.2 ghz. tones are situated at 177.5 mhz and 182.5 mhz. ? the pin_0dbfs lev el is reduced by 6 db when idac1 fs is reduced to 2 ma. ? the imd performance remains below ?80 dbc until an attenuator setting of 9 db. ? further increases in the two - tone power lead to a corresponding steady decline in the imd performance due to the nonline arity of the attenuator. ? although not shown, the nsd performance centered about the if improves a few db with increased attenuation. 17 ?10 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 ?7 ?4 ?1 2 5 8 11 14 0 21 18 15 12 9 6 3 pin_0dbfs (dbm) worst imd (dbc) attenuator setting (db) pin_0dbfs_idac1fs = 2ma pin_0dbfs_idac = 4ma imd_idac1fs = 4ma imd_ idac1fs = 2ma 12348-047 figure 96 . imd com ponent degradation as two - tone centered at an if of 180 mhz is increased 1 db for every 1 db increase in a ttenuator setting , s uch t hat two - tone level remains at ?8 dbfs the effects of switching transients are another important consideration for agc implementations that digitally calibrate gain changes in the signal path of the receiver that can otherwise degrade the demodulation of the desir ed signals. figure 97 and figure 98 show the iq envelope response when the attenuator state is switched between 0 db and 6 db via an external control signal using the agc 2 input pin at a rate of 3.3 mhz. note that the settling response is dominated by the response of the digital filter (decimate by 12) and shows no signs of glitch. rev. 0 | page 33 of 86
AD6676 data sheet 1.00 0 0.25 0.50 0.75 160 140 120 100 80 60 40 normalized i/q magnitude (db) sample 12348-048 figure 97 . wide envelope response for 6 db a ttenuator step change with f data_iq = 250 msps, resul ting sample period of 4 ns 1.00 0 0.25 0.50 0.75 43 42 41 40 39 38 37 36 35 34 33 32 normalized i/q magnitude (db) sample 12348-049 figure 98 . zoom in envelope response for 6 db a ttenuator step change with f data_iq = 250 msps, resulting sample period of 4 ns clock synthesizer the AD6676 includes an on - chip clock synthesizer capable of generating the clock for the - adc and digital circuitry. the entire synthesizer is integrated on - chip, including the loop filter and vco. figure 99 shows a functional block diag ram of the various synthesizer subblocks along with the relevant spi registers. the clock synthesizer uses a standard integer - n architecture to generate a 2.94 ghz to 3.2 ghz adc clock from a 10 mhz to 320 mhz reference input. configuring the clock synthes izer requires numerous spi commands to program settings and to initiate calibrations. the s pi sequence to configure the AD6676 for a p articular operating mode, including the spi operations associated with the clock synthesizer, is most easily obtained from the software tool that comes with the AD6676 ebz development platform. this tool allows the spi sequence used to configure the AD6676 to be sav ed to a file for later use. note that if the clock synthesizer is used to supply the adc clock, the clock synthesizer must be configured first, before any other blocks are enabled. also note that because the clock synthesizer sequence involves calibration s, wait intervals or polling loops are needed to ensure that each calibration step completes before issuing the next spi command. table 27 lists an example spi sequence for a particular case where the reference fre quency ( f clk ) and adc clock rate ( f ad c ) are 200 mhz and f ad c = 3200 mhz, respectively. the remainder of this section describes the configuration of the clock synthesizer in detail. integrated loop filter to - adc and digital n counter reg 0x2a1 (lsb) reg 0x2a2 (msb) vddq enable clk syn reg 0x2ao 2 reg 0x2a5 direct rf clk option reg 0x2bb vddq vddq vddc r-divider charge pump reg 0x2ac reg 0x2ad reg 0x2bc pfd up dn 2 4 2 f pfd = 10mhz to 80mhz clk = 10mhz to 320mhz initial cal automatic level control cal reg 0x2ab reg 0x2bc vco 5.9ghz to 8.0ghz reg 0x2aa reg 0x2b7 12348-050 figure 99 . clk synthesizer block diagram rev. 0 | page 34 of 86
data sheet AD6676 r and n dividers the phase / frequency detector (pfd) requires a 10 mhz to 80 mhz clock. when f clk = 200 mhz, the r divider must be set to divide by 4 so that f pfd = f clk /r div = 50 mhz , which is within the supported range. table 11 shows the mapping from r div to the value of register 0x2bb. this register is set in step 6 of table 27 . table 11 . r divider settings for register 0x2bb r div register 0x2bb [7:6] 1 0b00 2 0b01 4 0b10 0.5 0b11 note that operating with the highest permissible f pfd minimizes the clock synthesizer reference spur because the pll filter bandwidth is fixed at 200 khz. for a sinusoidal clock input signal that has a limited input slew rate, op eration with an input frequency that is 2 or 4 the desired f pfd can also result in a slight improvement in phase noise performance. because the adc clock is obtained by dividing the vco clock by 2, the n - divider must be set according to n = 2 f ad c / f pfd =2 3.2 ghz/50 mhz =128 = 0x80 the value of n is programmed by writing the lsb (0x80) to register 0x2a1 and the msb (0x00) to register 0x2a2 and i s set in step 1 of table 27. charge pump current and calibration the charge pump current setting (register 0x2ac) is given by )) 1 10 33 . 1 , 63 (min( round 2 28 ? = adc pfd cp f f i (6) for the f ad c and f pfd values used in this example, icp evaluates to 25, or 0x19; this value is programmed in step 4 of table 27. the charge pump also must be calibrated during the clock synthesizer initialization phase. calibration is triggered via register 0x2ad the time required to complete the calibration is inversely proportional to the pfd frequency. for example, using f pfd = 1 0 mhz requires a maximum 4 ms wait period but increasing f pfd to 80 mhz decreases the maximum wait period by a factor of 8 to 0.5 ms. alternatively, poll bit 0 of register 0x2bc; charge pump calibration is complete when this bit is set. vco configuration a nd calibration vco configuration consists of writing to the spi registers in table 12 that control the vco core bias, temperature compensation, and varactor settings. these settings depend on the vco frequency and are optimized vi a characterization to ensure proper operation of the pll over supply and temperature. table 12 . vco configuration settings vs. f ad c f ad c (mhz) register 0x2aa register 0x2b7 2925 to 2950 0x37 0xf0 2950 to 3100 0x37 0xe0 3100 to 3200 0x37 0xd0 the vco also must be calibrated during the clock synthesizer initialization phase to ensure proper operation over its full temperature range. vco calibration is triggered via register 0x2ab with the amount of time required to complete the calibration again being inversely proportional to the pfd frequency. specifically, f pfd = 10 mhz requires a 2 ms wait period w h e reas f pfd = 80 mhz decreases the wait period by a factor of 8 to 0.25 ms. alternatively, poll bit 1 of register 0x2bc; vco cali bration is complete when this bit is clear. after the initialization process is complete, verify that bit 3 of register 0x2bc is set to confirm that the pll is locked. phase noise performance above the pll filter bandwidth of 200 khz, the internal vco limi ts the overall phase noise of the clock synthesizer. the vco phase noise performance shows a slight improvement at its low end of its f ad c operating range, as shown in figure 100 the phase noise for a particular if input frequency can be calculated using equation 5. pn f in_o ffset = pn f clk_offset + 20 log ( f if / f ad c ) (7) for example, the phase noise at 1 mhz offset for an f ad c of 3.2 ghz is approximately ?124 dbc/hz. an if input frequency of 200 mhz results in a 24 db improvement, thus the expected phase noise at 1 mhz offset is ?148 dbc/hz. C105 C107 C109 C111 C113 C115 C117 C119 C121 C123 C125 C127 C129 C131 C133 C135 5 2 1 0.2 0.4 0.6 0.8 clk syn phase noise f clk (dbc/hz) frequency offset (mhz) 2.95ghz 3.00ghz 3.10ghz 3.20ghz 12348-051 figure 100 . clock synthesizers typical phase noise for various f ad c values the repeatability of a device that is power cycled 10 times is shown in figure 101 . note that the measured data in this figure aligns with the expected results based on equation 5 and figure 100 . rev. 0 | page 35 of 86
AD6676 data sheet ?128 ?130 ?132 ?134 ?136 ?138 ?140 ?142 ?144 ?146 ?148 ?150 ?152 ?154 ?156 3 2 0.2 0.4 0.6 0.8 1 phase noise (dbc/hz) zero if frequency offset (mhz) mean ?125.81 ?140.93 ?144.14 ?146.48 std 0.23 0.11 0.11 0.10 pk-pk 0.71 0.32 0.37 0.39 12348-052 figure 101 . power cycle repeatability (10 attempts) of phase noise measurement for an if input frequency of 225 mhz and f clk = 2.94912 ghz with pll pfd = 61.44 mhz the phase noise variation over t emperature of a nominal device is shown in figure 102. ?128 ?130 ?132 ?134 ?136 ?138 ?140 ?142 ?144 ?146 ?148 ?150 ?152 ?154 ?156 3 2 0.2 0.4 0.6 0.8 1 phase noise (dbc/hz) zero if frequency offset (mhz) mean ?125.81 ?140.93 ?144.14 ?146.48 std 0.23 0.11 0.11 0.10 pk-pk 0.71 0.32 0.37 0.39 12348-052 figure 102 . typical temperature stability of clock synthesizer with the same conditions as figure 101 rev. 0 | page 36 of 86
data sheet AD6676 digital processin g blocks the AD6676 includes the following digital blocks between the - adc output and jesd204b transmitter core: ? an adc overload and recovery block immediately follows the adc. this circuitry quickly detects any adc instability from an overload event while ensuring fast recovery. ? a digital signal proce ssing block translates the real if signal from the - adc to a complex zero if, suitable for postprocessing by the host without loss of any dynamic range. this block includes both coarse and fine qddcs, along with a selectable fir decimation filter stage t hat provides decimation factors of 12, 16, 24, and 32. ? a peak detection and agc support block facilitates the implementation of an external agc control loop under the control of the host. note that the agc pins can also be repurposed for gpio functions. figure 103 shows a diagram of the digital functional blocks along with the spi configurable registers pertaining to these blocks. the following sections provide more insight into the operation of each of these functional blocks. m ore information pertaining to these spi registers can be found in table 32 through table 132 . band-pass ?$'& agc support agc4, agc3 agc2, agc1 reg 0x193 to 0x19e reset peak detector input adc overload recovery mix1 coarse qddc nco reg 0x141 reg 0x143 mix2 fine qddc nco reg 0x142 reg 0x144 reg 0x145 5 bits 2 16 bits 2 16 bits 27db attenuator (1db steps) 2 2 2 3 or 4 reg 0x188 to 0x18b, 0x18f gpio control option reg 0x1b0 to 0x1b4 attenuator control reg 0x180 to 0x184 dec_mode = 12, 16, 24 or 32 reg 0x140 12348-054 figure 103 . simplified block diagram of dig ital processing blocks rev. 0 | page 37 of 86
AD6676 data sheet digital signal proce ssing path the - adc provides a highly oversampled 5 - bit digital o utput representing the desired if signal pass band as well as the out - of - band shaped noise described earlier. referring to figure 104 , the digital signal pro cessing path translates this oversampled real if signal to a complex dc centered if signal, having a more manageable data rate suitable for transfer via the jesd204b interface. the qddc performs the real - to - complex frequency translation followed by digital filtering to re move the adc out - of - band noise, as well as any other undesired signal content , before decimation to a lower data rate without any loss of dynamic range. dc ? f adc /2 f adc /2 complex output after qddc ? f if f if dc ? f adc /2 f adc /2 adc real output desired signal adc noise image signal complex output after decimation ? f data_iq /2 f data_iq /2 dc complex output after filtering ? f adc /2 f adc /2 digital filter response 12348-055 figure 104 . digital signal processing path performs frequenc y translation to a zero if as well as filtering and downsampling quadrature digital downconversion digital downconversion occurs in two stages using a coarse and a fine qddc. as shown in figure 103 , the coarse qd dc resid es immediately after the - adc and the fine qddc follows the first decimation stage. the coarse qddc provides 6 - bit tuning resolution wh ereas the fine qddc provides 10 - bit tuning resolution. the composite tuning resolution is either f ad c /3072 or f ad c /409 6, depending on whether the first decimation stage is configured for 3 or 4 decimation, which in turn depends on the decimation mode selected as described in table 13 . for applications requiring finer tuning resolution to positi on the if signal exactly about dc, consider adding a finer resolution qddc in the host processor. table 13 . finite composite tuning resolution of coarse and fine nco dec_mode (register 0x140, bits[2:0]) decimation factor tuning r esolution tuning res. (mhz) at f ad c = 3 .072 gsps 1 32 f ad c /4096 0.75 2 24 f ad c /3072 1.00 3 16 f ad c /4096 0.75 4 12 f ad c /3072 1.00 the tuning frequency of the combined coarse and fine nco must be set such that the center of the if pass band is centered about dc. the coarse tuning nco is set via mix1_tuning wh ereas fine tuning nco is set via mix2_tuning[7:0]. use the following equations to calculate the decimal equivalent frequency setting of the nco for each register. ? ? ? ? ? ? ? ? = is a 6 - bit binary number representing the nco frequency setting in mix1_tuning. f if is the desired carrier frequency in hertz (hz). f ad c is the adc clock rate in hertz (hz). ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = is a 8 - bit twos complement number repre senting the nco frequency setting in mix2_tuning. m is 3072 for dec_mode = 2 and 4, or 4096 for dec_mode = 1 and 3. it is important to note the residue, f offset , between the desired f if and the AD6676 composite nco setting, f if _nco , because any offset may need to be compensated with an additional fine qddc located in the host processor. use the following equations to calculate both para meters: adc nco if f m mix2 mix1 f ? ? ? ? ? ? + = = f if C f if_nco (11) rev. 0 | page 38 of 86
data sheet AD6676 example calculate the nco mix1 and mix2 values along with f if _nco and f offset with the following AD6676 configuration: f if = 140 mhz, f ad c = 3200 mhz, and decimation factor of 16 (that is, f data_iq = 200 msps). ? substituting f if and f ad c values in equation 8 results in mix1 = 3. ? substituting these values in equati on 9 ( noting that m = 4096 for dec_mode = 3 results in mix2 = ?13 ) . ? substituting mix1 and mix2 values into equation 10 results in f if _nco = 139.84375 mhz. ? substituting f if and f if _nco values in equation 11 results in f offset = 156.25 khz. nco phase synchronizati on the AD6676 coarse and fine tuning ncos can be set to an initial phase after synchronization with an external sysref signal. the ini tial phase of the coarse tuning nco is set via mix1_init, with an lsb corresponding to 1/64 th of a cycle. the initial phase of the fine tuning nco is set via mix2_init _x , with an lsb corresponding to 1/1024 th of a cycle. digital filter modes the AD6676 digital filter path is designed to provide sufficient stop band rejection of the - adc shaped out - of - band noise as well as any spurious noise that otherwise might alias back into the desired pass band region after decimation and limit the actual nsd performance. the filter path supports decimation factors of 12, 16, 24, and 32 depending on the dec_mode setting. the complex output of the c oarse qddc feeds a pair of symmetrical fir decimation filters divided into three stages, as shown in figure 103 . the first stage is a decimate by 3 or by 4 filter, depending on whether the desired decimation factor is divisible by three. the second and third stages consists of two cascaded decimate by 2 filters with the third stage outputs supporting the decimate by 12 and by 16 options. a bypassable fourth stage provides the decimate by 24 and by 32 options. the normalized pass b and and wideband folded frequency response for each filter mode are shown in figure 105 through figure 113 . note the following observations: ? all filter responses provide a linear phase response over its p ass band. ? the usable if bandwidth depends on the dec_mode as well as the minimum acceptable pass band ripple and stop band rejection requirements. table 14 provides the normalized usable complex bandwidth vs. dec_mode for stop ban d rejections of greater than 85 db and 60 db. ? the last filter stage sets the usable bandwidth and stop band rejection because it has the most aggressive transition band specifications. for this reason, the decimation factors of 12 and 16 have the same nor malized usable bandwidths as does decimation factors of 24 and 32. ? wide if bandwidths (mhz) are supported when operating at lower decimation factors along with a high f ad c . ? it is worth noting that many applications requiring wider if bandwidth may tolerate reduced ripple and rejection as the digital filter response enters its transition region. the reason is that the - adc achievable nsd performance at the if pass band edges also degrades as its oversampling ratio is reduced, thus still dominating relativ e to any aliased noise due to reduced filter stop band rejection. table 14 . usable normalized complex bandwidth vs. decimation factor dec_mode decimation factor f data_iq bw (>85 db rejection) bw (>60 db rejection) 1 32 1 0.814 0.8 34 2 24 1 0.814 0.834 3 16 1 0.571 0.617 4 12 1 0.571 0.617 total pipeline latency the digital filter path dominates the latency of the AD6676 wh ereas the jesd204b phy adds a few samples of delay and the adc delay is a fraction of an output sample. the latency between the adc and digital filter output is fixed with the only nondeterministic delay being associated with the jesd204b p hy clock and lane fif os before synchronization. see the synchronization using sysref section for additional information. table 15 provides the nominal pipeline delay associated with each dec_mode. note th at although all dec_mode settings provide similar delays relative to the output data rate, f data_iq , applications that require shorter absolute time delays may consider using a lower decimation factor to reduce the absolute delay by 2. table 15. nominal pipeline latency vs. dec_mode (sample delay r elative to 1/ f data_iq ) dec_mode decimation factor jesd204 b lanes iq data output sample delay 1 32 1 34.2 2 24 1 34.2 3 16 2 32.3 4 12 2 32.3 rev. 0 | page 39 of 86
AD6676 data sheet 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 magnitude (db) frequency normalized to f data_iq 12348-056 figure 105 . pass band frequency response of decimate by 12 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 magnitude (db) frequency normalized to f data_iq 12348-057 figure 106 . pass band frequency response of decimate by 16 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 magnitude (db) frequency normalized to f data_iq 12348-058 figure 107 . pass band frequency response of decimate by 24 0 ?120 ?100 ?80 ?60 ?40 ?20 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 magnitude (db) frequency normalized to f data_iq minimum alias attenuation 85.5db 12348-059 figure 108 . folded frequency response of decimate by 12 shows alias rejection 0 ?120 ?100 ?80 ?60 ?40 ?20 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 magnitude (db) frequency normalized to f data_iq minimum alias attenuation 85.5db 12348-060 figure 109 . folded frequency response of decimate by 16 shows alias rejection 0 ?120 ?100 ?80 ?60 ?40 ?20 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 magnitude (db) frequency normalized to f data_iq minimum alias attenuation 85.5db 12348-061 figure 110 . folded frequency response of decimate by 24 shows alias rejection rev. 0 | page 40 of 86
data sheet AD6676 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 magnitude (db) frequency normalized to f data_iq 12348-062 figure 111 . pass band frequency response of decimate by 32 0 ?120 ?100 ?80 ?60 ?40 ?20 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 magnitude (db) frequency normalized to f data_iq minimum alias attenuation 88db 12348-063 figure 112 . folded frequency response of decimate by 32 shows alias rejection agc features and pea k detection in receive r applications, it is desirable to have a mechanism to reliably determine when the converter is about to be overdriven. the AD6676 - adc is based on a feedback loop that can be overdriven into a nonlinear region, resulting in oscillation. this oscillation persists until the - adc is reset and the overload condition is removed. typi cally, a receiver line up employs some form of agc that attempts to avoid this scenario. the AD6676 pipeline latency along with any additional overhead associated with the host proces sor (jesd204b rx phy) may limit the ability to design a fast reacting digital - based agc required by some applications. for this reason, the AD6676 includes the agcx pins that serve as digital input/ outputs to facilitate the implementation of a fast agc control loop under the control of the host. the agc4 and agc3 pins can be allocated to provide flag outputs after a programmable thresho ld has been exceeded, including an adc reset event, while the agc2 and agc1 pins can be used to control the on - chip attenuator. register 0x18f and register 0x193 through register 0x19e are used for agc purposes. peak detection and agc flags peak detection occurs at the output of the second stage decimation filter, as shown in figure 103 . detection at this stage represents a compromise between the accuracy of the peak detector, delay time and ability to measure large out - of - band si gnals. at this stage, the - adc output signal has been frequency translated to dc and its out - of - band noise sufficiently filtered for reasonable threshold detection accuracy down to ?12 dbfs peak signal levels. note that the peak detector monitors the peak power envelope response of the if input signal and calculates the peak power (that is, i 2 + q 2 ) expressed in dbfs with 12 - bit resolution. because the peak detector is monitoring the peak power at the output of the second stage decimation filter, it provides a wider frequency ra nge than what can be observed in the final iq data output. the first stage filter is decimate by 3 or by 4 ; therefore , the output of the second stage filter can be 1/6 th or 1/8 th of f ad c . figure 113 shows the normalized measuremen t bandwidth relative to the output rate of the second stage filter centered about its zero if . table 16 references the measurement bandwidth to f data_iq for the different decimation factors such that its absolute bandwidth can be e asily determined. for example, the ?1 db bandwidth for an f data_iq of 100 msps with decimate by 24 or by 32 is 200 mhz and remains at 200 mhz if the decimation factor is reduced to decimate by 12 or by 16. any droop occurring at the pass band edges, as wel l as the - adc stf, must be considered when setting thresholds. 0.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 magnitude (dbfs) frequency offset from if center (normalized to f iq@2nd stage filter ) ?0.35 ?0.25 ?0.15 ?0.05 0.05 0.15 0.25 0.35 12348-064 figure 113 . normalized pass band filter response seen by the peak detector table 16 . normalized measurement bandwidth of peak detector rela tive to output data rate, f data_iq dec_ mode decimation factor normalized measurement bandwidth relative to f data_iq ?0.5 db fs ?1.0 db fs ?2.0 db fs ?3.0 db fs 1 32 1.76 2.00 2.40 2.64 2 24 1.76 2.00 2.40 2.64 3 16 0.88 1.00 1.20 1.32 4 12 0.88 1.00 1. 20 1.32 rev. 0 | page 41 of 86
AD6676 data sheet the AD6676 allows the user to set three threshold settings that can trigger one of two possible flags. pkthrh0 and pkthrh1 are two upper threshold settings while lowthrh is a lower threshold setting. the threshold settings are 12 bits with an msb and lsb register assigned to each threshold. the 12 - bit decimal equivalent value can be calculated using equation 12. threshold = 35 84 + ( threshold setting in dbfs) 256/3 (12) where 0 dbfs corresponds to 3584 (0xe00) and ?6 dbfs corresponds to 3072 (0xc00). in the time domain, a 0 dbfs setting corresponds to a signal whose peaks observed at the i and q outputs can reach plus or minu s full scale . meaning, if the 16 - bit i and q output data are normalized such that its peak values correspond to 1, a 0 dbfs setting corresponds to a signal whose peak can reach the unit circle of a normalized i/q constellation diagram. the lowthrh _x regi ster has an associated dwell time of which the signal must remain below this threshold before a flag can be set. the dwell time is represented in exponential form to realize long dwell periods because the counter operates at f ad c /12 for decimate by 12 or 2 4 settings or f ad c /16 for decimate by 16 or 32 settings. the dwell time is set in the dwell_time_ mantissa register and dwell_time_exp register using equation 13 relative to 1/ f ad c . dwell time = n [ dwell_time_mantissa ] 2 ( dwell_time_exp ) (13) where: n = 12 for decimate by 12 or 24. n = 16 for decimate by 16 or 32. a flag function can be assigned using the flag0_sel register and flag1_sel register to indicate when any of the thresholds have been exceeded or if an adc reset event has occurred. these flags must also be enabled via the en_flag register such that a cmos level signal appears on the agc4 and agc3 pins where a logic high indicates when a threshold has been exceeded. the delay relative to the adc input when an agc threshold is exceeded to when t he flag signal goes high is dependent on the dec_mode setting selected. for a dec_mode value of 1 or 2 (decimate by 32 or 24), the delay equates to 8 to 9 output samples (1/ f data_iq ) . for dec_mode values of 3 or 4 (decimate by 16 or 12), the delay is 16 to 18 samples. the delay associated with an adc reset event is much shorter because it avoids the digital filter path. this delay is 1 sample for dec_mode values of 1 or 2 and 2 samples for dec_mode values of 3 and 4. note that the en_flag x bits provide the additional option of logically oring an adc reset event with an upper peak threshold event to provide an even faster output flag to the host processor indicating that the attenuation must be applied. this scenario applies to the extreme case where the en velope response of a blocker is exceedingly fast, such that the agc cannot react fast enough to the upper peak threshold setting flag to prevent overloading the - adc. figure 114 provides an example of how th e flag 0 and flag 1 assigned pins behave to the envelope response of an arbitrary if input signal. f lag 1 is assigned an upper threshold set by pkthrh1 _x , and flag 0 is assigned a lower threshold and dwell time set by lowthrh _x and dwell_time _x . the flag 1 indicator goes high when the pktthr1 _x threshold is exceed ed and returns low when the signal envelope falls below this threshold. the flag 0 indicator goes high only when the envelope of the signal remains below the lowthrh _x threshold for the designated dwell time. if the s ignal level exceeds the lowthrh _x threshold before the dwell time counter has expired, the dwell time counter resets again and the flag 0 indicator remains low until the conditions has been met. by offsetting the pktthr1 _x and lowthrh _x threshold settings as well as optimizing the dwell time setting, it may be possible to optimize the operation of an agc so that it react s to signal strength variation due to fading conditions as opposed to the peak to minimum response associated with digital modulated signa ls. if attenuator control via the agc2 and agc1 pins many agc implementations require fast gain control if the agc threshold is exceeded. the AD6676 provides two modes in which the if attenuator can be quickly changed via the agc x pins . use register 0x180, bit 0 , to select the mode. the first mode uses the agc 2 pin to switch between two attenuator settings that are user defined in regi ster 0x181 and register 0x182. the second mode uses the agc2 and agc1 pins to decrement and increment respectively the attenuation value in 1 db steps with pulsed inputs. the starting attenuator value is defined in register 0x183. the actual attenuator val ue can be read back via register 0x184. the first mode is used for the default AD6676 power - up setting with both register 0x181 and register 0x182 set to 0x0c. for applications that do not requi re if attenuator control but require a different attenuator setting, update both registers with the desired attenuator setting value such that the attenuator remains independent of the agc2 pin state, if it is left floating. note that connecting the unused agc2 and agc1 pi ns to vssd via 100 k? pull - down resistors is still the preferred method if these pins are unused. rev. 0 | page 42 of 86
data sheet AD6676 upper threshold (pktthr1) lower threshold (lowthrh) flag1 flag0 midscale dwell time timer reset by rise above lower threshold timer completes before signal rises above lower threshold dwell time 12348-065 figure 114 . example of flag behavior as signal envelope crosses upper and lower threshold settings gpio functionality the agcx pins can also be configured for basic gpio functionality via register 0x1b0 to register 0x1b4. register 0x1b0 determines which pins are used for gpio functionality, whereas register 0x1b1 determines if an agc pin serves as input or output. if the pin serve s as an output, register 0x1b2 determines the high or low state, and register 0x1b3 reads back the state of these designated output pins. lastly, if an agc x pin serves as an input, register 0x1 b4 reads back the state of this pin. power saving modes the AD6676 features two spi configurable and selectable power savings modes. the first mode is a sleep mode where the AD6676 is placed in a low power state for extended periods, and the second mode is a standby mode where the AD6676 enters a reduced power state but still keeps the jesd204b link and digital clocks active to ensure multichip synchronization (or fixed latency) during fast power cycling. both sleep mode and standby mode can be entered via a spi write operation to the pd_mode bits in the device_config register (register 0x002; bits[1:0]). note that , depending on whether sleep or standby mode is selected, various functional blocks within the - adc itself are either powered down, placed in a low bias state, or remain powered. the standby mode is also controllable via a user designated agcx pin for faster and more precise power cycling. this feature is particularly useful for tdd - based commu nication protocols, allowing the host processor to quickly power cycle the AD6676 during transmit bursts. the pd_pin_ctrl register (re gister 0x152) enables this feature as well as designates the agc pin. the standby register (register 0x150) powers down different functional blocks during standby mode. however, all functional blocks that a ffect the clock generation, distribution and the j esd204b link remain enabled to maintain constant latency while in standby. the only exception is stby_ vss2gen (register 0x150, bit 6) where a trade - off exists in power savings vs. wake - up time, depending on whether the negative voltage generator is placed in standby. table 17 shows the realized power savings for the different power savings modes at 3.0 gsps operation with the AD6676 configured for 125 msps iq output and the internal clock synthesizer e nabled. note that stdby_fast and stdby_slow correspond to whether the stby_ vss2gen bit is enabled or disabled during standby. note that an additional 18% power sav ings can be achieved when powering down the stby_ vss2gen bit . table 17 . power saving for 3.0 gsps operation with clksyn enabled and 125 msps iq rate (single jesd204b lane) power state at 3 gsps i vdd2 (ma) i vdd1 + , i vddc + i vddl (ma) i vddd (ma) p total (mw) % power savings 1 stdby_ slow 18 162 216 461 61 stdby_ fast 95 175 221 673 43 power down 2.6 25 29 64 n/a power up 146 433 310 1182 n/a 1 n/a means not applicable. although the AD6676 can enter into standby quickly, it does require a few microseconds to exit standby. figure 115 shows that the AD6676 can achieve a low power state within 100 ns. figure 116 and figure 117 show the wake - up time between the stdby_fast and stdby_slow cases to achieve 1% envelope settling accuracy being around 2.5 s and 11.5 s , respectively. the phase response is not shown because it settles faster than the envelope response. note that the digital data path is enabled for these time dom ain figures such that the setting time responses can be observed. rev. 0 | page 43 of 86
AD6676 data sheet 1.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10.0 10.0 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 11.0 normalized envelope output time (s) AD6676 enters standby within 100ns 12348-066 figure 115 . fast power - down response when the AD6676 is placed in standby 1.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 14.0 14.5 15.0 15.5 16.0 16.5 17.0 17.5 18.0 18.5 19.0 normalized envelope output time (s) 1% settling time = 2.5s 12348-067 figure 116 . settling time for stdby_fast with the stby_ vss2gen enabled for fastest recovery, approximately 2.5 s to 1 % 1.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0 2 4 6 8 10 12 14 16 18 20 normalized envelope output time (s) 1% settling time = 11.5s 12348-068 figure 117 . settling time for stdby_slow with s tby_ vss2gen in standby for additional power savings, approximately 11.5 s to 1 % introduction to the jesd204b interface the jesd204b interface reduces the pcb area for data interface routing yet enabling the use of smaller packages for converter and lo gic devices. the AD6676 digital output complies with the jedec standard no. jesd204b, serial interface for data converters . jesd204b i s a protocol to link the AD6676 to a digital processing device over a serial interface . t he AD6676 supports link rates of up 5.333 gbps while operating with two output lanes in support of a maximum i/q data rate ( f data_iq ) of 266.67 msps. note that a two output lane c onfiguration is always required for decimation factors of 12 and 16. jesd204b overview jesd204b data transmit block assembles the parallel data from the adc into frames and uses 8 - bit/10 - bit encoding as well as optional scrambling to form serial output dat a. lane synchronization is supported through the use of special characters during the initial establishment of the link and additional synchronization is embedded in the data stream thereafter. a jesd204b receiver is required to complete the serial link . f or additional details on the jesd204b interface, refer to the jesd204b standard. because the AD6676 provides 16 - bit complex iq data, i ts jesd204b transmit block effectively maps the output of two virtual adcs (m = 2) over a link. the link is configurable for either single or dual lanes with each lane providing a serial data stream via a differential output. the jesd204b specification ref ers to a number of parameters to define the link and these parameters must match between the AD6676 jesd204b transmitter and receiver. the following parameters describe a jesd204b link: ? s = samples transmitted per single converter per frame cycle ( AD6676 value = 1) ? m = number of converters per converter device ( AD6676 value = 2) ? l = number of lanes per converter device ( AD6676 value can be 1 or 2) ? n = converter resolution ( AD6676 value = 16) ? n = total number of bits per sample ( AD6676 value = 16) ? cf = number of control words per frame clock cycle per converter device ( AD6676 value = 0) ? cs = number of control bits per conversion sample ( AD6676 value = 0) ? k = number of frames per multiframe (configurable on the AD6676 up to 32) ? hd = high density mode ( AD6676 value = 0) ? f = octets per frame ( AD6676 value = 2 or 4, dependent on l = 2 or 1) ? t = tail bit ( AD6676 value = 0) ? scr = scrambler enable o r disable (configurable on the AD6676 ) rev. 0 | page 44 of 86
data sheet AD6676 fig ure 118 shows a simplified block diagram of the AD6676 jesd204b link mapping the 16 - bit i and q outputs onto the two separate lanes. other configurations are also possible, such as combining the i and q outputs onto a single lane ( f data_iq 153.6 msps) or changing the mapping of the i and q output paths. in any case, the 16 - bit i and q data are each broken into two octets ( eight bits of data). bit 15 (msb) through bit 8 are in the first octet. the second octet contains bit 7 through bit 0 (lsb) . the four resulting octets (2 i octets and 2 q octets) may be scrambled. scrambling is optional but is available to avoid spectral peaks when transmitting similar digital data patterns. the scrambler uses a self synchronizing polynomial - based algorit hm defined by the equation 1 + x 14 + x 15 . the descrambler in the receiver must be a self synchronizing version of the scrambler polynomial. the four octets are then encoded with an 8 - bit/10 - bit encoder. the 8 - bit/10 - bit encoder takes eight bits of data (an octet) and encodes them into a 10 - bit symbol. figure 119 shows how the 16 - bit i or q data is taken from the final decimation stage, formed into octets , the two octets are scrambled, and how the octets are encoded into two 10 - bit symbols. adc sysref syncinb i converter 0 q converter 1 serdout0?, serdout0+ serdout1?, serdout1+ lane swap (spi reg 0x1e1) jesd204b link control (l.m.f.m.s) (spi reg 0x1c3 to 0x1c9) framer swap (spi reg 0x1e1) 12348-069 figure 118 . transmit link simplified block diagram 8-bit/10-bit encoder (0x1e4) serdout0 serdout1 serializer adc symbol0 symbol1 adc test patterns (reg 0x1e5) jesd204b sample construction jesd204b test patterns (0x1e5) frame construction jesd204b test patterns (reg 0x1e5, reg 0x1f8 to reg 0x1ff) jesd204b test patterns (reg 0x1e5, reg 0x1f8 to reg 0x1ff) scrambler 1 + x 14 + x 15 (optional via 0x1c3) a b c d e f g h i j a b c d e f g h i j a b i j a b i j 16-bit 12348-070 figure 119 . digital formatting of jesd204b lanes transport layer physical layer data link layer tx output sample construction frame construction scrambler alignment character generation 8-bit/10-bit encoder crossbar mux serializer processed samples from adc sysref syncinb 12348-071 figure 120 . data flow rev. 0 | page 45 of 86
AD6676 data sheet functional overview the flo wchart in figure 120 shows the flow of data through the j esd204b hardware from the sample input to the physical output. the processing is divided into layers that are derived from the osi model widely u sed to describe the abstract ion layers of communications systems. these are the transport layer, the data link layer, and the physical layer (serializer and output driver). transport layer the transport layer packs the data into jesd204b frames, which are mapped to 8 - bit octets that are sent to the data link layer. the transport layer mapping is controlled by rules derived from the link parameters. the AD6676 uses no tail bits in the transport layer because the output of its iq digital data path is considered two virtual 16- bit converters. data link layer the data link layer is responsible for the low level functions of passing data across the link. these include o ptional data scrambling, inserting control characters for lane alignment/ monitoring, and encoding 8 - bit octets into 10 - bit symbols. the data link layer also send s the initial lane alignment sequence (ilas), which contains the link configuration data, and is used by the receiver to verify the settings in the transport layer. physical layer the physical layer consists of the high speed circuitry clocked at the serial clock rate. for the AD6676 , the 16 - bit i and q data are converted into one or two lanes of high speed differential serial data. jesd204b link establ ishment the AD6676 jesd204b tx interface operates in subclass 0 or subclass 1 as defined in the jedec stan dard no. 204b (j uly 2011 ) specification. the link establishment process is divided into the following ste ps: code group synchronization, ilas, and user data. code group synchronization (cgs) and syncinb code group synchronization (cgs) is the process where the jesd204b receiver finds the boundaries between the 10 - bit symbols in the stream of data. during the cgs phase, the jesd204b transmit (jesd tx) block transmits /k28.5/ characters. the receiver must locate /k28.5/ characters in its input data stream using clock and data recovery (cdr) techniques. the receiver issues a synchronization request by asserting a low signal on the syncinb pins of the AD6676 . the jesd tx begins to send /k/ characters. after the receiver has synchronized, it th en deasserts its syncinb signal, causing it to go high. the AD6676 then transmits an ilas on the following lmfc boundary. for more in formation on the cgs phase, see the jedec standard no. 204b (july 2011) , s ection 5.3.3.1. the syncinb pin operation options are controllable via spi registers. although the syncinb input is configured for a cmos logic level on its positive pin by defau lt, it can also be configured for a differential lvds input signal on its positive/ negative pins via register 0x1e7. the polarity of the syncinb input signal can also be inverted via register 0x1e4. initial lane alignment sequence (ilas) the ilas phase fo llows the cgs phase and begins on the next lmfc boundary. the ilas consists of four multiframes, with a /r/ character marking the beginning and an /a/ character marking the end. the ilas begins by sending an /r/ character followed by a data ramp starting w ith the value , 0 , over four multiframes. on the second multiframe, the link configuration data is sent, starting with the third character. the second character in the second multiframe is a /q/ character to confirm that the link configuration data follows. all undefined data slots are filled with ramp data. the ilas sequence is never scrambled. the ilas sequence construction is shown in figure 121 . the four multiframes include the following: ? multiframe 1: begins with an /r/ charac ter (/ k28.0 /) and ends with an /a/ character (/ k28.3 /) . ? multiframe 2: begins with an /r/ character followed by a /q/ (/ k28.4 /) character, followed by link configuration parameters over 14 configuration octets (see t able 18 ), and ends with an /a/ character. many of the parameter values are of the notation of n ? 1. ? multiframe 3: begins with an /r/ character (/ k28.0 /) and ends with an /a/ character (/ k28.3 /) . ? multiframe 4: begins with an /r/ character (/ k28.0 /) and ends with an /a/ character (/ k28.3 /) . user data and error detection after the ilas is complete, the user data is sent. normally, in a frame all characters are user data. however, to monitor the frame clock and multiframe clock synchronization, there is a mechanism for replacing characters with /f/ or /a/ alignment characters when the data meets certain conditions. these conditions are different for unscrambled and scrambled data. the scrambling operation is disabled by default, but may be enabled via regis ter 0x1c3. rev. 0 | page 46 of 86
data sheet AD6676 for scrambled data, any 0xfc character at the end of a frame is replaced by an /f/ and any 0x7c character at the end of a multiframe is replaced with an /a/. the jesd204b receiver checks for /f/ and /a/ characters in the received data s tream and verif ies that they only occur in the expected locations. if an unexpected /f/ or /a/ character is found, the receiver uses dynamic realignment or asserts the syncinb signal for more than four frames to initiate a resynchronization. for unscrambl ed data, if the final character of two subsequent frames is equal, the second character is replaced with an /f/ if it is at the end of a frame, and an /a/ if it is at the end of a multiframe. insertion of alignment characters may be modified using spi. th e frame alignment character insertion is enabled by default. more information on the link controls is available in the spi register descriptions for register 0x1e0 to register 0x1e6. 8 - bit/10 - bit encoder the 8 - bit/10 - bit encoder converts 8 - bit octets into 10- bit symbols and inserts control characters into the stream when needed. the control characters used in jesd204b are shown in table 18 . the 8 - bit/10 - bit encoding ensures that the signal is dc balanced by using the same number of ones and zeroes across multiple symbols. note that the 8 - bit/10 - bit interface has an invert option available in register 0x1e4 that has the same effect of swapping the differential output data pins. k k r d d a r q c c d d a r d d a r d d a d start of ilas start of link configuration data end of multiframe start of user data 12348-072 figure 121 . initial lane a lignment sequence table 18 . control characters used in jesd204b including running disparity values abbreviation control symbol 8 - bit value 10- bit value (rd = ?1) 10- bit value (rd = +1) description /r/ k28.0 000 11100 001111 0100 11 0000 1011 start of multiframe /a/ k28.3 011 11100 001111 0011 110000 1100 lane alignment /q/ k28.4 100 11100 001111 0010 110000 1101 start of link configuration data /k/ k28.5 101 11100 001111 1010 110000 0101 group synchronization /f/ k28.7 111 11100 001111 1000 110000 0111 frame alignment rev. 0 | page 47 of 86
AD6676 data sheet rev. 0 | page 48 of 86 physical layer input/outputs digital inputs the AD6676 physical layer consists of consists of two digital differential inputs, sysref and syncinb, whose equivalent input circuits are shown in figure 61 and figure 64. these inputs must be dc-coupled to their respective drivers because they are or can be aperiodic. the syncinb input is logic compliant to both cmos and lvds via register 0x1e7, bit 2, with cmos being the default. note that the syncinb input includes an internal 100 termination resistor when lvds is selected. the optional sysref input can be used for multichip synchronization or establishing a repeatable latency between the AD6676 and its host. the sysref receiver circuit must be disabled if not used (register 0x1e7 = 0x04) to prevent potential false triggering if the input pins are left open. the sysref input does not include an internal 100 termination resistor; thus, an external differential termination resistor must be included if this input is used. the sysref input is logic complaint to lvpecl, lvds, and cmos. digital outputs, timing and controls the AD6676 physical layer consists of digital drivers that are defined in the jedec standard no. 204b (july 2011). these cml drivers are powered up by default via register 0x1e2. the drivers utilize a dynamic 100 internal termination to reduce unwanted reflections. a 100 differential termination resistor at each receiver input results in a nominal 300 mv p-p swing at the receiver. the AD6676 jesd204b differential outputs can interface with custom asics and fpga receivers, providing superior switching performance in noisy environments. single point-to-point network topologies are recommended with receiver inputs having a nominal differential 100 termination. the common mode of the digital output automatically biases itself to half the vddhsi supply of 1.1 v (vcm = 0.55 v), thus making ac coupling the preferred coupling method to the receiver logic as shown figure 122. dc coupling can be considered if the receiver device shares the same vddhsi supply and input common-mode range. serdoutx+ v ddhsi serdoutx? output swing = 300mv v cm = vddhsi/2 100? receiver 100 ? differential trace pair 0.1f 0.1f 12348-073 figure 122. ac-coupled digital output termination example timing errors caused by a degraded eye diagram at the receiver input can often be attributed to poor far end termination or differential trace routing. these potential error sources can be reduced by using well controlled differential 100 traces with lengths below six inches that connect to receivers with integrated differential 100 resistors. figure 123, figure 124, and figure 125 show examples of the digital output data eye, time interval error (tie) jitter histogram, and bathtub curve for one AD6676 lane running at 5.333 gbps. the format of the output data is twos complement by default. the output data format can be changed via register 0x146. 400 ?400 ?300 ?200 ?100 0 100 200 300 ?150 150 100 50 0 ?50 ?100 voltage (mv) time (ps) 12348-503 eye: all bits, offset: ?0.0055 uis: 4000; 1059998, total: 4000; 1059998 figure 123. digital outputs data eye with external 100 terminations at 5.333 gbps in accordance to lv-oif-11g-sr mask 9000 8000 7000 6000 5000 4000 3000 2000 1000 0 ?5 ?4 ?3 ?2 ?1 0 5 4321 hits time (ps) 12348-504 figure 124. digital outputs histogram with external 100 terminations at 5.333 gbps 1 1 ?2 1 ?4 1 ?6 1 ?8 1 ?10 1 ?12 1 ?16 1 ?14 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.50.4 0.3 0.20.1 ber uis 12348-505 figure 125. digital outputs data bath tub with external 100 terminations at 5.333 gbps
data sheet AD6676 preemphasis preemphasis enables the receiver eye diagram mask to be met in conditions where the interconnec t insertion loss does not meet the jesd204b specification. the preemphasis feature is controlled via register 0x1ef and must be used only when the receiver cannot recover the clock due to excessive insertion loss. under normal conditions, it is disabled to conserve power. additionally, enabling and setting too high a deemphasis value on a short link may cause the receiver eye diagram to fail or lead to potential emi issues. for these reasons, consider the use of preemphasis only in instances where meeting t he receiver eye diagram mask is a challenge. see the register memory map section for details. serializer pll this pll generates the serializer clock that is equal to the jesd204b lane rate. the on - chip controller automatically con figures the pll parameters based on the user specified iq data rate ( f ad c /m) and number of lanes. the status of the pll lock can be checked via the pll_lck status bit in register 0x2dc. this read only bit lets the user know if the pll has achieved a lock f or the specific setup. configuring the jesd 204b link the AD6676 has one jesd204b link. the serial outputs (serdout0 and serdout1) a re part of one jesd204b link. the basic parameters that determine the link setup are: ? l is the number of lanes per link ? m is the number of converters per link ? f is the number of octets per frame the maximum and minimum specified lane rates for the AD6676 are 5 .333 gbps and 3.072 gbps, respectively. for this reason, the AD6676 supports a single lane interface for iq data rates ( f data_iq ) from 76.8 msps to 13 3. 3 msps and a two lane interface from 153.6 msps to 266.7 msps. the lane line rate is related to the jesd204b par ameters using the following equation: ( ) l f rate line lane data_iq = dec f f adc data_iq = table 19. jesd204b output configurations no. virtual converters supported (same as m) f data_iq (msps) jesd serial line rate l m f s hd n n' k 2 76.8 to 133.3 40 f data_iq 1 2 4 1 0 16 16 for f = 4, k 5 153.6 to 266.7 20 f data_iq 2 2 2 1 0 16 16 for f = 2, k 9 rev. 0 | page 49 of 86
AD6676 data sheet synchronization usin g sysref the AD6676 uti lizes the sysref input to provide synchronization for the jesd204b serial output and to establish a fixed phase reference for the decimation filters and the nco within the qddc. synchronization options are configurable via register 0x1e8. when initially s ynchronizing, the absolute phase offset relative to the input clock applied to the clk pins depends on internal clock phases and therefore ha s an uncertainty of 1 adc clock cycles . a clock tree diagram is shown in figure 126 wit h an internal clock signal, dig_clk, used to ultimately sample the sysref signal. note that the sysref setup and hold times are defined with respect to the rising sysref edge and rising clk (or clk+ with the clock synthesizer disabled) edge, as shown i n figure 2 . after the sysref signal is sampled, the phase remains locked to the same relative internal adc_clk phase offset until the AD6676 is intentionally reset or its clock or power interrupted. note the following considerations when using sysref for synchronization. ? the sysref pulse width must be at least two adc_clk periods. ? bit 3 of register 0x2bb mu st be set low when synchronizing with the clock synthesizer enabled. in this case, that sysref is sampled on the rising edge of ref_clk to allow for significant margin in setup and hold time. this s ynchronization signal is then sampled again with the inte rnally generated dig_clk. ? because sysref is ultimately sampled with an internal clock greater than 1 ghz, it can be difficult to maintain synchron ization of the clock and sysref distribution in a system over supply and temperature variations, as well cu mulative jitter affects. for this reason, it is suggested to utilize the one shot sysref mode to avoid unnecessary resetting of the jes204b link. ? if continuous sysref is still preferred, it is recommended to use the sysref_win_neg and sysref_win_ pos bit s in register 0x1ea to allow for slight variation in sysref timing relative to dig_clk. ? a phase variance of 1 adc clock cycles ultimately results in fractions of a sample when referenced to the iq output data rate, f data_iq , depending on the decimation f actor. for example, for a decimation factor of 32, the phase uncertainty is expressed as 1/32 samples relative to f data_iq . clock synthesizer f out = 5.9ghz t o 6.4ghz 2 d q q d q q clk sysref rf_clk reg 0x2a5 adc_clk dig_clk to ? adc and digital t o digi t a l t o synchroniz a tion circuit r y reg 0x2bb ref_clk 2 12348-131 figure 126 . block diagram showing options of sampling the sysref input signal with the clock synthesi zer disabled or enabled rev. 0 | page 50 of 86
data sheet AD6676 applications informa tion analog input conside rations equivalent input impedance and s11 the AD6676 benign in put structure along with its low drive level requirements facilitates interfacing it to external driver circuitry. figure 127 shows the equivalent parallel impedance for attenuator settings of 0 db and 6 db. note that the slight v ariation in impedance between the different attenuator settings is an error source affecting the absolute accuracy of the attenuator settings. the AD6676 input also displays excellent s11 return loss over a wide frequency range , as shown in figure 94. 62 61 60 59 58 57 56 55 54 53 52 10 9 8 7 6 5 4 3 2 1 0 0 100 200 300 400 500 600 800 1000 700 900 shunt r () shunt c (pf) frequency (mhz) 12348-703 shunt r with attenuator = 0db shunt r with attenuator = 6db shunt c with attenuator = 0db shunt c with attenuator = 6db figure 127 . typical equivalent parallel impedance of ain for a ttenuator = 0 and 6 db settings input driver and filter considerations the input driver requirements , along with any additional filtering , are application dependent. additional filtering may be considered if any large signal content or blockers falling above or below the if pa ss band of interest can cause desensitization by either increasing the adc noise or spur floor. below the if pass band, the AD6676 is most sensitive to second harmonic content that is typically ind uced by the driver stage itself due to its limited ip2 performance. the a d6676 second - order non linearity contribution is typically on par with a balanced mixer and well below the contribution of a single - ended amplifier stage (with output balun) used for vhf applications. table 20 shows the measured f 1 + f 2 spurious level and equivalent iip2 for different ifs when dual tones a re inject ed at ? 6 dbfs levels and at if/2. table 20 . harmonic levels when dual tone s = ?6 dbfs of pin_0dbfs level i s situated at if/2 if ( mhz ) l ex t ( nh ) pin_0dbfs ( dbm ) dual tone input power ( dbm ) f 1 + f 2 spur ( db c ) equivalent ip2 ( dbm ) 200 43 ? 2.5 ? 8.5 ? 69.5 6 1 250 19 ?2.2 ?8.2 ?68.3 60 300 19 ? 2.2 ? 8.2 ? 7 3 6 5 350 10 ?2.2 ?8.2 ?66.3 58.5 400 10 ? 2.2 ? 8.2 ? 68.5 60 above the if pass band, the AD6676 is sensitive to high frequency blockers that can increase the noise floor due to jitter or generate an image component that fa lls back into the pass band. the AD6676 is also fairly insensitive to spurious tones falling in the alias regions occurring at f ad c f if because the AD6676 provides over 50 db of alias rejection. table 21 shows the typical alias rejection fo r different f adc and if combinations. because mixer s often produce fixed large spurious at m lo as w ell as its sum term of lo + f rf , determine if any of these spurs can fall in the alias regions and if so, add the appropriate level of filtering to suppre ss them below the receivers required spurious level. table 21 . typical alias rejection for different if and adc combinations f ad c ( mhz ) if ( mhz ) f ad c ? if alias rej ection ( dbc ) f ad c + if alias rejection (dbc) 2000 150 58 59 2400 2 00 53 54 2800 300 51 59 3200 400 51 59 because the required attenuation of out - of - band signal signals is application dependent , evaluate the AD6676 under the desired application conditions to understand the effects and determine what amount of filtering is required. in practice, a simple third - order low - pass roofing filter can provide adequate additional suppression against spurs fall ing in the alias regions as well as large signal signals falling a few 100 m h z above the if pass band. note that t he AD6676 ebz incl udes a n optional 500 m h z third - order low - pass filter ( tdk mea1210d501r) that may suffice for m any applications . this small , 0302 size differential filter is also available with lower frequency options. its effect on the pass band flatness is mimimal but pr ovides provides additional suppression beyond 700 mhz . as shown in figure 128 as well as in the alias region as shown in table 22. rev. 0 | page 51 of 86
AD6676 data sheet 5 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 0 100 200 300 400 500 600 800 1000 700 900 normalized stf response (dbfs) frequency (mhz) 12348-704 without tdk lpf with tdk lpf figure 128 . tdk f ilter has minimal e ffect on t he pass band if response table 22 . typical alias rejection for different if and adc combinations with tdk 500 mhz low - pass filter added f ad c (mhz) if (mhz) f ad c ? if alias rejection (dbc) f ad c + if alias rejection (dbc) 2000 150 82 83 2400 200 77 85 2800 300 71 83 3200 400 74 81 a 1:1 balun is required in applications where the last amplification stage is single - ended with a z out of 50 ?. this is typically th e case in a vhf receiver application where a gain block, such as the adl554x series, precedes the AD6676 for preamplification. vin+ vin? 1nf 1nf adl554x vhf signal 1:1 balun (maba-007159) AD6676 12348-077 figure 129 . rf line - up for direct sampling vhf application for many rf receiver applications, this differential signal may originate from a rf - to - if mixer whose output imped ance often falls within a 50 ? to 200 ? range. a low order matching network that also serv es as a low - pass roofing filter can compensate for the mismatch impedance. it is worth noting that the impedance mismatch between a source/load mismatch of 200 ?/60 ? and 100 ?/60 ? is approximately 1.5 db and 0.3 db, respectively. this low mismatch loss may be tolerable for some applications seeking a wide, low ripple if pass band, especially considering the loss of a higher order matching network with finite q compon ents. lastly, i t is possible to reduce the adc maximum input power requirements slightly to compensate for this low loss with minimal loss in dynamic range. other receiver applications in the vhf band may prefer that the AD6676 directly digitize the signal. typically, the radio lineup may include a low nf gain block whose single - ended output is converted to a differential output via an ac - coupled balun. the amplitude/phase balance requirements of balun can be relaxed (compared to traditional pipeline adcs) because the even order harmonics that are sensitive to balance fall outside the pass band . note that the second harmonic of the g ain block still must fall outside the vhf pass band so that it can also be digitally filtered. some additional considerations pertaining to the analog input are as follows: ? ac coupling with 10 n f or greater capacitors to the vin input is required to a mai ntain 1 v common - mode voltage. note that this capacitor provides a high - pass response with the AD6676 input impedance and thus must be sized accordingly for low if applications to prevent excessive droop on the lower pass band response. ? a series 10 ? resistor and 0.1 f decoupling capacitor is recommended between the 2.5 v supply and first resonators to provide additional filtering of supply induced noise and adc common - mode currents. ? the feedback dac (operating up to 3.2 ghz) also genera tes high frequency content (that is, images, clock feedthrough and shaped noise ) that is ideally absorbed by the internal source follower. due to its finite impedance at the higher frequencies, a small amount of this undesired signal content leaks through the attenuator path back to the vin input. passive mixers are particularly susceptible to this signal content due to poor isolation between the if and rf ports , but a simple third - order roofing filter typically proves sufficient to suppress these adc arti facts while also suppressing the larger m n artifacts of the mixer . note that this filter must be designed as two single - ended pi filters with shunt capacitors located next to the vin pins to steer this undesired signal content to ground. clock input co nsiderations the AD6676 - adc operates with an internal adc clock rate ( f ad c ) between 2.0 gsps to 3.2 gsps. the clock signal can originate from an external clock source or , alternatively , from its on - chip clock synthesizer. consider a n external clock source if the on - chip synt hesizer phase noise or spurious level is not deemed sufficient or if the desired f ad c falls below the 2.94 ghz to 3.2 ghz range of the vco . referring to figure 60 , the self - biased clock receiver is configured as ei ther a differential or single - ended receiver , depending on whether the clock synthesizer is disabled . in either case , the external clock source must be ac coupled to the AD6676 clk input and meet the minimum specified input level and slew rate. also, clock jitter and phase noise must always be a concern in selecting the clock source. rev. 0 | page 52 of 86
data sheet AD6676 w hen the clock synthesizer is enabled, the clk inp ut s are connected to cmos inverter s as shown in figure 60. these inverters are self - biased at approximately 0.55 v and present an input resistance exceeding 1.2 k ? . a s ingle - ended clock source need only be ac coupled to the clk + input because the inverter output for clk ? input is not used . note that a differential clock source can also be ac coupled to the clk pins while still meeting the minimum vol tage swing at the clk+ input . when the clock synthesizer is disabled, the clk inputs are connected to a high - speed differential clock receiver with on - chip 100 ? termination to simplif y interfacing to cml, lvpecl, or sinusoidal clock sources. the clock signal is typic ally ac - coupled t o the clk+ and clk? pins via a rf balun or capacitors. these pins are biased internally (see figure 60 ) at approximately 700 mv and require no external bias. the equivalent shunt impedance of the c lk input is shown in figure 130. it is recommended to utilize a 100 ? differential transmission line to route the clock signal to the clk+ and clk? pins due to the high frequency nature of the signal. 130 50 60 70 80 90 100 110 120 1.0 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 2.0 2.5 3.5 4.0 3.0 real shunt () capacitance (pf) frequency (ghz) 12348-705 real shunt capacitance shunt figure 130 . equivalent s hunt d ifferential i nput i mpedance of the clk p ins with the c lock s ynthesizer d isabled figure 131 show s a single - ended clock solution for the AD6676 when its clock synthesizer is disabled. the low phase noise single - ended source c an be from an external vcxo . a ceramic rf chip 1:2 ratio balun create s the differential clock input signal. t he balun must be specified to have low loss (that is, less t han 2 db) at the clock frequency of interest. the single - ended clock source must be capable of 0 dbm drive capability to ensure adequate signal swing into the clock input. AD6676 clk+ clk? clock input 100pf 100pf 100pf jt 4000bl14100 12348-078 figure 131 . balun - coupled differential clock a single - ended cmos or differential ac - coupled pecl/lvds clock signal can be delivered via clock generation and distributio n ics such as the analog devices ad9520 , ad9522 , ad9523 , or ad9524 . figure 132 show s a simple differential interface in which the AD6676 interfaces to the pe cl output available from the i c s such as t he ad9520 , ad9522 , ad9523 , ad9524 , and the adclk9xx series, such as the adclk905 , adclk907 , and adclk925 . note that many ics in the ad95 x x family include on - chip vco s with excellent phase noise characteristi cs that can support clock frequencies over the 2.0 ghz to 2.8 ghz range. AD6676 clk+ clk? 10nf 240? 240? pecl driver 12348-081 10nf ad95xx or adclk9xx figure 132 . differential pecl sample clock alternatively, pll clock synthesizers with on - chip vco s such as the adf435x series and hmc1034 also make excellent clock sources with phase noise characteristics that are typically better than those found on clock generation ic with on - chip vcos. the cml outputs of these devices allow a simple interface as shown in figure 133. figure 134 compares the close in phase noise between the adf4351 , the AD6676 c lock s ynthesizer , and the r&s sma100a for a near full - scale sine wave at 300 mhz. note that the phase noise improvement offered by the high quality rf generator only becomes ev ident below 400 k hz when compared to the adf4351 . clk+ clk? ref out 1+ ref out 1? ref out 1+ ref out 1? 1nf 1nf adf4351 3.9nh AD6676 0.8v p-p div-by-2 n pll vco fref v vco 12348-079 figure 133 . differential cml driver from the adf4351 ?110 ?115 ?120 ?125 ?130 ?135 ?140 ?145 ?150 ?155 0.01 0.1 1 phase noise @ if = 300mhz (dbc/hz) frequency offset (mhz) AD6676 clk syn adf4351 r&s sma100a 12348-080 figure 134 . close in phase n oise comparison when the adf4351 or r&s sma100a used as clock sources vs. the AD6676 clock synthesizer (if = 300 mhz, bw = 40 mhz, f ad c = 3.2 ghz, l = 19 nh) rev. 0 | page 53 of 86
AD6676 data sheet if frequency plannin g t he - adc can achieve exceptional sfdr performance over a wide if frequency range because its high oversampling ratio prevents low order harmonics from aliasing into the if pass band. higher order harmonics that do alias back are typically of much lower m agnitude, with the shuffling option further reducing their levels. however, finite isolation between the - adc and the digital block cause s additional spurious signals that are a function of the output data rate, f data_iq , and input frequency, f in . speci fically, the feedback dacs in the - adc suffer from digital contamination of its clock signal. therefore, the same equation used to predict spurious locations on high speed dacs with digital interpolation filters applies. equation 15 defines this relatio nship with the spur location falling at f mn . f mn = ( m f data_iq ) ( n f in ) (15) where: m is the digital induced harmonic content from internal clocks. n is the harmonics from the - adc. when n = 0, signal independent spurs fall at integer multiples of f data_iq . table 23 shows the measured m f data_iq spurious levels (dbfs) for different if frequencies and decimation factors with f data_iq equal to 100 msps and 200 msps. all of the m f data_iq regions display low spurious with the exception of 200 mhz. this is because a large portion of digital circuitry is clocked at f ad c /16 for dec_modes of 1 and 3 or f ad c /12 for dec_modes of 2 and 4. as a result, the m = 2 spur is dominant when operating at the higher decim ation factors of 32 and 24 wh ereas the m = 1 spur is dominant when operating at the lower decimation factors of 16 and 12. when n = 1, signal dependent spurs falls at integer multiples of f data_iq . these m n spurs are called images because they have a 1 :1 relationship in amplitude and frequency with the input signal, f in . note that the magnitude of some images can also vary slightly between power cycles , due to different phase relationships among internal clock dividers upon device initialization. figure 135 shows a normalized image graph (relative to f data_iq ) showing the image location relative for a given input frequency. when n > 1, spurious content is often at lower magnitude than other spurious thus often can be ignored. th e exception is when f in falls below the if pass band such that its lower order harmonics may fall within the pass band (that is, if/2 and if/3). 4.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 normalized image location normalized input frequency m = 6 m = 7 m = 8 m = 5 m = 3 m = 4 m = 2 m = 2 m = 3 m = 1 12348-082 figure 135 . image location for different m factors normalized to f data_iq table 23. measured spurious levels at different ifs where m f data_iq falls on for f data_iq of 100 msps and 200 msps f data_iq spurious levels (dbfs) if = 100 mhz if = 200 mhz if = 300 mhz if = 400 mhz 100 msps dec_mode = 1 AD6676 offers a wide range of suitable ifs for a given output data rate, f data_iq . even ifs that are situated in a region where the worst m f data_iq spurious condition described in table 23 can be used because they remain at a fixed location and remain signal independent. similar to the lo feedthrough issue in a direct conversion iq receiver, a slow digital tracking loop in the host processor can be used to nullify it. figure 136 and figure 137 show a case where the if of 200 mhz was selected for an f data_iq of 200 msps and 100 msps such that dominant spur falls exactly at the if center. as shown in figure 135 , the if is positioned at a normalized f data_iq of 1 or 2 for 200 msps and 100 msps operation, thus explaining why the image term is m = 2 or 4. note that the image spur is quite low for m = 2 and can be further improved by selecting a higher decimation factor (dec_mode of 3 vs. 1) that results in the m = 4 image. rev. 0 | page 54 of 86
data sheet AD6676 0 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 150 160 170 180 190 200 210 220 230 240 250 spur (dbfs/nbw) input frequency (mhz) f in = 180mhz (?1dbfs) m = 2, n = ?1 spur @ ?88dbc m = 1, n = 0 spur @ ?81dbfs nbw = 9.2khz 12348-083 figure 136 . image spur for f data_iq = 200 msps (dec_mode = 3) attributed to m = 2, n = ?1 0 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 150 160 170 180 190 200 210 220 230 240 250 spur (dbfs/nbw) input frequency (mhz) f in = 180mhz (?1dbfs) m = 4, n = ?1 spur @ ?96dbc m = 1, n = 0 spur @ ?81dbfs nbw = 9.2khz 12348-084 figure 137 . reduction in image spur w hen f data_iq is r educed to 100 msps if pass band regions that remain free of any of these spurs exist in the following regions for a swept input tone across its pass band: ( m ? 0.5) f data_iq < if pass ban d < m f data_iq (16) or m f data_iq < if pass band < ( m + 0.5) f data_iq (17) note that because these spur free regions have a bandwidth of 0.5 f data _iq , it is often desirable to use a higher f data _iq rate (that is, lower decimation factor) to support larger if bands. figure 138 shows a spur free region swept sfdr less than ?95 dbfs with f data_iq = 200 msps and bw = 100 mhz with the if now centered at 250 mhz. selecting an if s ituated at 350 mhz and bw = 100 mhz also produces similar results. 0 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 200 210 220 230 240 250 260 270 280 290 300 spur (dbfs/nbw) input frequency (mhz) f in = 238mhz (?1dbfs) nbw = 9.2khz 12348-085 figure 138 . digital induced spurs for an if t h at i s c entered b etween f data_iq and 1.5 f data_iq with f data_iq = 200 msps pcb design guideline s the design of the pcb is critical in achieving the full performance of the AD6676 . the AD6676 ebz evaluation board, used for characterizing the AD6676 ac performance, serves as an example of a possible layout. figure 139 shows the topside pcb layout of the region surrounding the AD6676 where all the critical analog input/outputs, digital input/outputs, and passive components reside. note the following obser vations: ? the pcb is a 6 - layer board based on fr4 dielectric that avoids any expensive options, such as micro, hidden or blind vias, thus allowing cost effective manufacturing. ? critical analog and digital high speed signal paths are routed on the first laye r with controlled impedances. the lower speed cmos digital input/outputs are placed on the back side sixth layer. ? a single solid ground plane is used as the second layer underneath the AD6676 . the dielectric spacing is 8 mil to establish controlled impedances with the critical signal layer above. ? the third and fourth layers are dedicated power planes used to isolate the different AD6676 supply domains, and the fifth layer is a solid ground plane. the dielectric spacing between the second and third layer and the fourth and fifth layer is 3 mil to increase the distributed decoupling capacitance for each supply domain. ? special consideration was given to via placement, ground fill, and power supply plane layout to main low thermal and electrical impedances. ? all critical p assive components, such as dc blocking and power supply decoupling capacitors, are 0201 size and placed on top side of the pcb. two 0201 decoupling capacitors (0.001 f and 0.1 f) are placed adjacent to supply pins with the lower value placed closer to th e AD6676 . ? the analog 1.1 v supply pins of the AD6676 share a common 1.1 v supply domain and are tied together below the device. ? vss2out (pin g7) must be connected to vss2in (pin f6) on the top side layer of the pcb. rev. 0 | page 55 of 86
AD6676 data sheet rev. 0 | page 56 of 86 12348-086 figure 139. AD6676ebz pcb layout example additional information specifically pertaining to the wlcsp package considerations can be found in the an-617 application note . this application note covers pcb design guidelines, assembly, reliability, and rework in detail. powering the AD6676 the AD6676 requires the following analog and digital power supplies with no restrictions on the power supply sequencing order: ? an analog 2.5 v and 1.1 v supply ? a digital 1.1 v and digital input/output supply of 1.8 v to 2.5 v the current consumption from the different analog and digital supply domains does not vary much over the specified 2.0 ghz to 3.2 ghz adc clock rate range nor the digital decimation factor and number of jesd204b lanes used. table 24 shows the dependency of a typical device as these settings are modified with the if and bw remaining fixed at 250 mhz and 75 mhz, respectively. figure 140 shows the recommended method used on the AD6676ebz where a universal 3.3 v supply is available. note that various analog and digital supply domains within the AD6676 are grouped together to reduce the external ldo requirements. a high efficiency step-down regulator, such as the adp2164 , is used to generate a 1.6 v output that drives separate low drop-out ldos for the analog vdd1 and digital vddd supplies. adp2164 adp1752-2.5 adp1752-1.8 adp1752-1.1 vddd, vddhsi vdd2, vdd2nv vddio adp1752-1.1 vdd1, vddc, vddq 1.6v 3.3v 12348-087 figure 140. low noise power solution for the AD6676 separate ldos for the 1.1 v analog and digital supplies are used to provide greater isolation between these critical supply domains as well as reduce the ir drops across ferrite beads that provide further isolation. high quality ldos that exhibit better pssr characteristics at the switching regulators operating frequency are preferable. on the analog 1.1 v supply, amplitude modulation can result in phase modulation via the clock supplies of the AD6676 (vddc, vddq). figure 141 and figure 142 show the measured sideband level in dbc that results if a 1 mv p-p continuous wave tone has frequencies common among switching regulators are injected onto the 1.1 v and 2.5 v analog supplies. note that the sideband level increases at roughly 6 db per octave in if frequency for the 1.1 v supply domain case because the supply noise results in pm modulation that affects the clock jitter. ? 74 ?76 ?78 ?80 ?82 ?84 ?86 ?88 ?90 100 200 400 500 300 150 350 450 250 sideband level (dbc) if input frequency (mhz) 12348-706 400mhz 800mhz 1600mhz 3200mhz figure 141. sideband spur level fo r 1 mv p-p, continuous wave tone injected on analog 1.1 v supply domain ? 94 ?96 ?98 ?100 ?102 ?104 ?106 ?108 ?110 100 200 400 500 300 150 350 450 250 sideband level (dbc) if input frequency (mhz) 12348-707 400mhz 800mhz 1600mhz 3200mhz figure 142. sideband spur level fo r 1 mv p-p, continuous wave tone injected on analog 2.5 v supply domain
data sheet AD6676 table 24 . current consumption variation as f adc is varied from 3.2 ghz to 2.0 ghz supply current conditions f clk unit 3.2 ghz 2.8 ghz 2.4 ghz 2.0 ghz i vdd1 + i vddl not applicable 371 364 357 351 ma i vddc + i vddq not applicable 60 59 56 52 ma i vdd2 + i vdd2nv not applicable 143 140 139 139 ma i vddd decimate by 16 152 144 131 100 ma decimate by 32 155 150 135 106 ma i vddhsi two lane 168 168 168 158 ma one lane 166 167 167 161 ma on the digital 1.1 v supply, amplitude modulation on the jesd204b high speed serializer supply (vddhsi) can negatively impact the eye opening of t he digital data output stream. for these reasons, low noise ldos, such as the adp1752 , that have a worst - case accuracy of 2% over line, load, and temperature are used for the analog vdd2 and vdd1 supplies. the same regulator is used for the digital vddd for its low dropout characteristics, power supply rejection ratio , and load capability. although the digital vddd is used for the less critical vddio supply, a smaller, lower cost regulator such as the adp121 , can also be used to supply 1.8 v. AD6676 start - up initialization on power - up of the AD6676 , a host processor is required to initialize and configure the AD6676 via its spi port. figure 143 shows a flow chart of the sequential steps required to bring the AD6676 to an operational state. the number of spi writes and total initialization time is dependent on whether the clock syn - thesizer is used, as well as any additional configuration associated with the agc features or its pin configurations. note that wait states are required during different steps in t he initialization process to allow various actions, such as calibration and tuning, to be completed before moving to the next step. table 26 shows the minimum spi writes required to enable the AD6676 . note the following in the sequence of steps shown in table 26: ? the example spi writes pertain to the following settings: f adc = 3200 mhz, f o = 300 mhz, bw = 100 mhz, f data_iq = 2 00 msps with decimate by 16, and f ref = 200 mhz with the clock synthesizer enabled. ? step 3 refers to table 28 for necessary spi writes when the clock synthesizer is enabled or disabled resp ectively. example agc parameters are included in table 29 but are nonessential to device operation. ? the reson1 calibration for the adc occurs first with default dec_mode setting. dec_mode is updated to the user specified setting p rior to jesd204b calibration. ? adc and jesd204b calibration and initialization must be successful on first attempt. however, s tep 2 4 and step 30 are included to provide coverage against external events (supply or clock glitch) that can corrupt this process. 12348-088 hardware or software reset AD6676 operational program configuration settings jesd204b configuration adc parameters run adc cal + jesd204b initialization calibration + tuning initialize clk syn initialize rf clk path wait (2ms) wait (400ms) clk syn? no yes cal ok? no yes adc cal/tune error (make two more attempts) all registers returned to default program optional settings agc configuration adc shuffler run reson1 cal with dec_mode=1 wait (400ms) cal ok? no yes reson1 tune error (make two more attempts) program decimation mode figure 143 . flowchart for initialization and configuration of the AD6676 rev. 0 | page 57 of 86
AD6676 data sheet the AD6676 evb software gui has an option that automatically generates and saves the series of spi writes in the format of a .csv file as shown in table 25 . this is the preferred method of generating the spi write sequence because the software also includes look - up tables used with the associated clock synthesizer operations to set the frequency dependent parameters. note that the spi writes asso ciated with the agc can be removed (if not used) or modified. table 25 . example of saved file format in microsoft? excel ? reg_addr write 0x000 0x99 0x2a5 0x08 0x2a0 0x7d 0x2ab 0xc5 #wait wait 2 ms table 26 . spi initialization example, f clk = 3.2 ghz, f if = 25 0 mhz, bw = 100 mhz, mrgn_ l = mrgn_u = 10 mhz, f data_iq = 200 msps with decimate by 16 step address (hex) write value comments 1 0x000 0x99 software reset, 4 - wire spi . 2 not applicabl e not applicable wait 2 ms for spi initialization after reset. 3 not applicable not applicable clk path or clk syn initialization (see table 28 for using external rf clock; refer to table 27 for using in ternal clk syn. ) 4 0x1e7 0x04 s elect lvds input for syncinb receiver. 5 0x1c0 0x01 jesd204 (did = 1 , optional). 6 0x1c1 0x05 jesd204 (bid = 5 , optional). 7 0x1c3 0x01 jesd204b (scr = 0, l = 2). 8 0x1c4 0x01 jesd204b (f = 2). 9 0x1c5 0x0f jesd204b (k = 16). 10 0x100 0x80 set f ad c to 3200 mhz. 11 0x101 0x0c 12 0x102 0xfa set the if to 250 mhz. 13 0x103 0x00 14 0x104 0x64 set the bw to 100 mhz. 15 0x106 0x13 set l ext to 19 nh. 16 0x107 0x0a set mrgn_ l to 10 mhz. 17 0x108 0x 0a set mrgn_u to 10 mhz. 18 0x10a 0x40 set idac1 fs to 4 ma , resulting in pin_0dbfs = ? 2 dbm . 19 0x116 0x0a initiate res on 1 calibration. 20 not applicable not applicable wait 250 ms for f clk = 3.2 ghz. note that the wait time scales with f clk proportionally such that the wa it = 400 ms for f clk = 2 ghz. 21 not applicable not applicable read back register 0x117 to see if bit 0 has been set to 1 indicating adc calibration is complete. if not, proceed to step 22. 22 0x11a 0x01 force end of calibration (toggle bit 0). 0x11a 0 x00 23 not applicable not applicable return to step 19 and attempt again. make two attempts before breaking out of loop if the calibration problem persists. 24 0x140 0x03 set dec_mode to user defined setting of decimate by 16. 25 0x116 0x37 calibrate and initiate adc; set - up and initiate jesd204b. 26 not applicable not applicable wait 250 ms for f clk = 3.2 ghz. note that wait time scales with f clk proportionally such that the wait = 400 ms for f clk = 2 ghz. 27 not applicable not applicable read back r egister 0x117 to see if bit 0 has been set to 1 indicating adc calibration is complete. if not, proceed to step 28. 28 0x11a 0x01 force end of calibration (toggle bit 0). 0x11a 0x00 29 not applicable not applicable return to step 2 5 and attempt again. make two attempts before breaking out of loop if the calibration problem persists. 30 not applicable not applicable i nsert the optional agc and non - default s huffler settings (see table 29 and table 26 for an exam ple) . rev. 0 | page 58 of 86
data sheet AD6676 table 27 . spi clk syn initialization example, f clk = 3.2 ghz, f ref = 200 mhz (suitable for decimation by 16) step address write value comments 1 0x2a1 0x80 set the integer - n value . 2 0x2a2 0x00 3 0x2ac 0x19 set the charge pump current (see table 12) . 4 0x2aa 0x37 configure the vco . 0x2b7 0xd0 5 0x2bb 0xb d set the reference divider to div = 4 , such that f pfd = 50 mhz (see table 11) . 6 0x2a0 0x7d enable clksyn and the adc clock . 7 0x2ab 0xc5 start vco calibration . 8 not applicable not applicable wait at least 400 ns because f pfd = 50 mhz . register 0x2bc , bit 1 = 0 indicates the vco calibration is done . 9 0x2ad 0x80 start charge pump calibration 10 not applicable n ot applicable wait at least 800 ns since f pfd = 50 mhz . register 0x2bc, bit 0 = 1 indicates the charge pump is done. register 0x2bc, bit 3 = 1 confirms the pll is locked . table 28 . spi f clk initialization step address write valu e comments 1 0x2a5 0x05 select rf clock path 2 0x2a0 0xc0 enable rf clock receiver and adc clock table 29 . spi agc initialization example step address write value comments 1 0x181 0x00 set atten_value_pin0 to 0 db. 2 0x182 0x 00 set atten_value_pin1 to 0 db. 3 0x19e 0x13 enable flag1 and 0 on agc 4 and agc 3 pins , respectively. also, logical or of adc reset with a peak detect threshold flag. 4 0x19b 0x04 select agc flag 0 above peak threshold 0 . 5 0x19c 0x 0 6 select agc f lag 1 below l ow t hreshold . 6 0x193 0x00 peak threshold 0 set to ?3 dbfs . 7 0x194 0x0d 8 0x197 0x00 low threshold s et to ?15 dbfs . 9 0x198 0x09 10 0x199 0x01 low t hreshold d well t ime m antissa . 11 0x19a 0x02 low t hreshold d well time e xponent . table 30 . spi shuffler initialization e xample step address write value comments 1 0x342 0x3f shuffle every two clock cycles with a threshold of 3. 2 0x343 0xff rev. 0 | page 59 of 8 6
AD6676 data sheet serial port interfac e (spi) spi register map des cription the AD6676 contains a set of programmable registers (described in the register memory map section) that initialize and configure the device for its intended appl ication. note the following points when programming the AD6676 spi registers: ? registers pertaining to similar functions are typically grouped together and assigned adjacent addresses. ? bits that are undefined within a register must be assigned a 0 when writing to that register. ? do not write to registers that are undefined. ? a hardware or software reset is recommended on power - up to place s pi registers in a known state. a spi initialization routine is required as part of the boot process. see table 26 for an example procedure. reset issuing a hardware or software reset places the AD6676 spi registers in a known state. both types of resets are similar in that they place spi registers to their default states as described in table 32 , with the notable exception that a software reset does not affect register 0x000. a hardware reset can be issued from a host or external supervisory ic by applying a low pulse with a minimum width of 40 ns to the resetb pin (pin g6). resetb can a lso kept be left open if unused because it has an internal pull - up resistor. after issuing a reset, the spi initialization process need only write to registers that are required for the boot process as well as any other register settings that must be modif ied, depending on the target application. although the AD6676 does feature an internal power on reset (por), it is still recommended t hat a software or hardware reset be implemented shortly after power - up. the internal reset signal is derived from a logical or operation from the internal por signal, the resetb pin, and the software reset state. a self clearing software reset can be issue d via the reset bit (register 0x00 , bit 7). it is also recommended that the bit settings for bits[7:4] be mirrored onto bits[3:0] for the instruction cycle that issues a software reset. table 31 . spi registers pertaining to spi opt ions address (hex) bit description 0x000 7 software reset spi 6 enable spi lsb first 4 enable 4 - wire spi operation the serial port of the AD6676 shown in figure 144 has a 3 - or 4 - wire s pi capability, allowing read/write access to al l registers that configure the internal parameters of the device. it provides a flexible, synchronous serial communication s port, allowing easy interface to most industry - standard fpgas and microcontrollers. the 1.8 v to 2.5 v serial input/output is compatible with most synchronous transfer formats . AD6676 spi port sdo (pin h6) sdio (pin k8) sclk (pin k7) csb (pin j6) 12348-089 figure 144 . AD6676 spi port the default 4 - w ire spi interface consists of a clock (sclk), serial port enable ( csb) , serial data input (sdio), and serial data output (sdo). the inputs t o sclk, csb , and s dio contain a schmit t trigger centered about vddio/2. the maximum frequency for sclk is 40 mhz. the sdo pin is active only during the transmission of data and remains three - stated at any other time . a 3 - wire spi interface can be enabled b y clearing the sdio_dir bit (register 0x000, bit 4). this causes the sdio pin to become bidirectional such that output data only appears on the sdio pin during a read operation. the sdo pin remains three - stated in a 3 - wire spi interface. instruction header information msb lsb i_15 i_14 i_13 i_12 i_01 i_00 r/ w a14 a13 a12 a1 a0 a 16 - bit instruction header must accompany each read and write operation. the msb is a r/ w indicator bit with logic high indicatin g a read operation. the remaining 15 bits specify the address bits to be accessed during the data transfer portion. the eight data bits immediately follow the instruction header for both read and write operations. for write operations, registers change imm ediately on writing to the last bit of each transfer byte. the AD6676 serial port can support both most significant bit (msb) first and least significant bit (lsb) first data formats. figure 145 illustrates how the serial port words are formed for the msb first and lsb first modes. the bit order is controlled by the lsb_f irst bit (register 0x0 0 0, bit 6). the default value is 0, msb first. when the lsb_first bit is set high, the serial port interprets both instruction and data byte lsbs first. rev. 0 | page 60 of 86
data sheet AD6676 sclk sdata r/w a1 a0 d7 1 d6 1 d1 n d0 n data transfer cycle instruction cycle csb a14 a13 sclk sdata r/w a1 a0 d7 1 d6 1 d1 n d0 n data transfer cycle instruction cycle csb a14 a2 12348-090 figure 145 . spi timing, msb first (upper) and lsb firs t (lower) figure 146 illustrates the timing requirements for a write operation to the spi port. after the serial port enable (csb) signal goes low, data (sdio) pertaining to the instruction header is read on the rising edges of t he clock (sclk). to initiate a write operation, the read/not write bit is set low. after the instruction header is read, the eight data bits pertaining to the specified register are shifted into the sdio pin on the rising edge of the next eight clock cycle s. figure 147 illustrates the timing for a 3 - wire read operation to the spi port. after csb goes low, data (sdio) pertaining to the instruction header is read on the rising edges of sclk. a read operation occurs if the read/not w rite indicator is set high. after the address bits of the instruction header are read, the eight data bits pertaining to the specified register are shifted out of the sdio pin on the falling edges of the next eight clock cycles. f igure 148 illustrates the timing for a 4 - wire read operation to the spi port. the timing is similar to the 3 - wire read operation with the exception that data appears at the sdo pin only, wh ereas the sdio pin remains at high impedance throughout the operat ion. the sdo pin is an active output only during the data transfer phase and remains three - stated at all other times. lastly, the spi port must not be active during periods when the full dynamic performance of the converter is required. because the sclk, c sb, and sdio signals are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on - board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the AD6676 to keep these signals from transitioning at the converter input pins and causing unwanted spurious signals. d7 d6 a0 d1 a14 t s sclk sdio t sclk t low t high t ds t dh r/w d0 t h csb a13 12348-091 figure 146 . spi write operation timing d7 d6 a0 d1 a14 t s sclk sdio t sclk t low t high t ds t dh r/w d0 t z a2 a1 t access csb 12348-092 figure 147 . spi 3 - wire read operation timing a0 csb a14 t s sclk sdio t sclk t low t high t ds t dh r/w a2 a1 t access d7 d6 d1 sdo d0 t z 12348-093 figure 148 . spi 4 - wire read operation timing rev. 0 | page 61 of 86
AD6676 data sheet rev. 0 | page 62 of 86 register memory map and details register memory map note that all address and bit locations that are not included in table 32 are not currently supported for this device. table 32. register summary reg name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x000 spi_config sw_reset lsb_first reserved sdio_dir sdio_dir reserved lsb_first sw_reset 0x18 0x002 device_config reserved pd_mode 0x00 rw 0x003 chip_type chip_type 0x03 r 0x004 chip_id0 chip_id0 0xbb r 0x005 chip_id1 chip_id1 0x00 r 0x006 grade_revision revision grade 0x00 r 0x00c vendor_id0 vendor_id0 0x56 r 0x00d vendor_id1 vendor_id1 0x04 r bp - adc configuration settings 0x100 fadc_0 fadc_0 0x10 rw 0x101 fadc_1 fadc_1 0x0e rw 0x102 fif_0 fif_0 0x2c rw 0x103 fif_1 fif_1 0x01 rw 0x104 bw_0 bw_0 0x3c rw 0x105 bw_1 bw_1 0x00 rw 0x106 lext lext 0x14 rw 0x107 mrgn_l mrgn_l 0x05 rw 0x108 mrgn_u mrgn_u 0x05 rw 0x109 mrgn_if mrgn_if 0x00 rw 0x10a idac1_fs idac1_fs 0x40 rw bp - adc calibration/profile 0x115 cal_ctrl reserved cal_profile 0x00 rw 0x116 cal_cmd reserved init_ntf_op init_jesd reson1_cal flash_cal init_adc tune_adc 0x00 rw 0x117 cal_done reserved cal_done 0x00 rw 0x118 adc_profile reserved adc_profile 0x00 w 0x11a force_end_cal reserved force_end_cal 0x00 rw digital signal path 0x140 dec_mode reserved dec_mode 0x01 rw 0x141 mix1_tuning reserved mix1_tuning varies rw 0x142 mix2_tuning mix2_tuning varies rw 0x143 mix1_init reserved mix1_init varies rw 0x144 mix2_init_lsb mix2_init_lsb 0x00 rw 0x145 mix2_init_msb reserved mix2_init_msb 0x00 rw 0x146 dp_ctrl reserved not_2s_compl 0x00 rw power control 0x150 standby reserved stby_ vss2gen stby_clk_pll stby_jesd_ pll stby_jesd_ phy stby_framer stby_datapath stby_digclk 0x02 rw 0x151 pd_dig reserved pd_framer pd_datapath pd_digclk 0x00 rw 0x152 pd_pin_ctrl reserved pd_pin_en reserved pd_pin_sel 0x00 rw 0x250 stby_dac stby_dac 0xff rw attenuator 0x180 atten_mode reserved atten_mode 0x00 rw 0x181 atten_value_pin0 atten_value_pin0 0x0c rw 0x182 atten_value_pin1 atten_value_pin1 0x0c rw 0x183 atten_init atten_init 0x00 rw 0x184 atten_ctl att_pin reserved atten_read 0x0c r adc reset control 0x188 adcre_thrh reserved adcre_thrh 0x05 rw 0x189 adcre_pulse_len reserved adcre_pulse_len 0x01 rw 0x18a atten_step_re reserved atten_step_re 0x06 rw peak detector and agc flag control 0x18f adc_unstable reserved clear_unsta ble flag unstable flag 0x00 rw 0x193 pkthrh0_lsb pkthrh0_lsb 0x00 rw 0x194 pkthrh0_msb reserved pkthrh0_msb 0x00 rw 0x195 pkthrh1_lsb pkthrh1_lsb 0x00 rw
data sheet AD6676 reg name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x196 pkthrh1_msb reserved pkthrh1_msb 0x00 rw 0x197 lowthrh_lsb lowthrh_lsb 0x00 rw 0x198 lowthrh_ msb reserved lowthrh_msb 0x00 rw 0x199 dwell_time_mantissa dwell_time_mantissa 0x00 rw 0x19a dwell_time_exp reserved dwell_time_exp 0x00 rw 0x19b flag0_sel reserved flag0_sel 0x00 rw 0x19c flag1_sel reserved flag1_sel 0x00 rw 0x19e en_flag reserved en _or reserved en_flag1 en_flag0 0x00 rw gpio c onfiguration 0x1b0 force_gpio reserved force_gpio 0x00 rw 0x1b1 force_gpio_out reserved force_gpio_out 0x00 rw 0x1b2 force_gpio_val reserved force_gpio_val 0x00 rw 0x1b3 read_gpo reserved read_gpo 0x00 r 0 x1b4 read_gpi reserved read_gpi 0x00 r jesd204b i nterface 0x1c0 did did 0x00 rw 0x1c1 bid reserved bid 0x00 rw 0x1c3 l scr reserved l 0x00 rw 0x1c4 f f 0x0 3 rw 0x1c5 k reserved k 0x 1f rw 0x1c6 m m 0x0 1 rw 0x1c9 s reserved s 0x00 rw 0x1cb res1 res1 0x00 rw 0x1cc res2 res2 0x00 rw 0x1d0 lid0 reserved lid0 0x00 rw 0x1d1 lid1 reserved lid1 0x0 1 rw 0x1d8 fchk0 fchk0 0x44 rw 0x1d9 fchk1 fchk1 0x 45 rw 0x1e0 en_lfifo reserved en_lfifo 0x00 rw 0x1e1 swap reserved swap_conv reserved swap_lane 0x00 rw 0x1e2 lane_pd ilas_delay reserved lane_pd 0x00 rw 0x1e3 mis1 reserved test_sample_en lsync_en ilas_mode faci_disable reserved 0x14 rw 0x1e4 sync_pin reserved sync_pin_inv reserved inv_10b reserved 0x00 rw 0x1e5 test_gen reserved test_gen_sel test_gen_m ode 0x00 rw 0x1e6 kf_ilas kf_ilas 0x00 rw 0x1e7 sync in b_ctrl reserved pd_sysref_rx lvds_sync in b reserved 0x00 rw 0x1e8 mix_ctrl reserved mix_use_2nd mix_next mix_all reserved use_2nd_ sysref next_sysref all_sysref 0x00 rw 0x1e9 k_offset reserved k_offs et 0x00 rw 0x1e0 en_lfifo reserved en_lfifo 0x00 rw 0x1ea sysref sysref_win_neg sysref_win_pos 0x00 rw 0x1eb ser1 ser_drv_ps reserved 0x1c rw 0x1ef pre - emphasis ser_emp_ps1 ser_emp_idac1 ser_emp_ps0 ser_emp_idac0 0x00 rw adc c lock s ynthesizer 0x2a0 c lksyn_enable en_extck en_adc_ck en_synth en_vco_ ptat en_vco _alc en_vco en_override_ cal en_override 0x00 rw 0x2a1 clksyn_int_n_lsb int_n_lsb[7:0] 0x 80 rw 0x2a2 clksyn_int_n_msb reserved int_n_msb[10:8] 0x00 rw 0x2a5 vco_cal_reset reserved vco_cal_ rese t reserved 0x00 rw 0x2aa clksyn_vco_bias reserved bias_tempco reserved bias 0x 37 rw 0x2ab clksyn_vco_cal init_alc_value alc_dis reserved id_synth 0xc0 rw 0x2ac clksyn_i_cp reserved i_cp 0x 19 rw 0x2ad en_cp_cal en_cp_cal reserved 0x00 0x2b7 clksyn_vc o_var vco_var reserved 0x d 0 rw 0x2bb clksyn_r_div r_div reserved sysref_ ctrl clkin_imped reserved 0x b 9 rw 0x2bc clksyn_status reserved pll_lck reserved vco cal busy cp cal done 0x00 r 0x2dc jesdsyn_status reserved pll_lck reserved 0x00 r adc a daptiv e s huffler control 0 x 340 shuffle_ctrl reserved en_adaptive_ shuffle 0x0 3 rw 0x34 2 shuffle_threg_0 shuffle_th2 shuffle_th1 0x f5 rw 0x34 3 shuffle_threg_1 shuffle_th4 shuffle_th3 0x ff rw rev. 0 | page 63 of 86
AD6676 data sheet register details spi configuration register address: 0x000, reset: 0x 18, name: spi_config table 33 . bit descriptions for spi _config bits bit name description reset access 7 sw_reset self - clearing bit causing software reset when set. software reset returns all spi registers to default state. 0 rw 6 ls b_first when set, causes input and output data to be orientated as lsb first, per spi standard. 0 4 sdio_dir when set, causes spi interface to be 4 - wire with output data appearing on the sdo pin. 1 this register uses the first four bits to configure sp i interface/format thus bit 0, bit 1, and bit 3 should be a mirror image of b it 7, bit 6 , and bit 4. device configuration register address: 0x002, reset: 0x00, name: device_config table. bit descriptions for device_config bits bit name description reset access [7 :2] reserved 0x0 rw [1:0] pd_mode power - down/standby control 00 = normal operation 01 = not used 10 = standby mode 11 = sleep (power - down) mode 0x0 rw chip type register address: 0x003, reset: 0x03, name: chip_type table 34 . bit descriptions for chip_type bits bit name description reset access [7:0] chip_type chip type: high - speed adc. 0x03 r chip id 0 register address: 0x004, reset: 0x bb , name: chip_id0 table 35 . bit descriptions for chip_id0 bit s bit name description reset access [7:0] chip_id0 chip id low byte. 0xbb r chip id 1 register address: 0x005, reset: 0x00, name: chip_id1 table 36 . bit descriptions for chip_id1 bits bit name description reset access [7:0] chip_ id1 chip id high byte. 0x00 r rev. 0 | page 64 of 86
data sheet AD6676 chip grade/revision register address: 0x006, reset: 0x00, name: grade_revision table 37 . bit descriptions for grade_revision bits bit name description reset access [7:4] revision 0x0 r [3:0] grade 0 x0 r vendor id 0 register address: 0x00c, reset: 0x56 , name: vendor _ id0 table 38 . bit descriptions for vendor _ id0 bits bit name description reset access [7:0] vendor_id0 0x56 r vendor id 1 register address: 0x00d, reset: 0x04 , n ame: vendor _ id1 table 39 . bit descriptions for vendor _ id1 bits bit name description reset access [7:0] vendor_id1 0x04 r adc clk frequency lsb register address: 0x100, reset: 0x10 , name: fadc_0 table 40 . bit descriptions for fadc_0 bits bit name description reset access [7:0] fadc_0 lower 8 - bits of 16 - bit value that defines the adc clk frequency to 1 mhz resolution. for example, the fadc_1 and fadc_0 settings for a 3 2 00 mhz clk frequency would be 0x0c and 0x8 0 , respectively. 0x10 rw adc clk frequency msb register 1 address: 0x101, reset: 0x0e , name: fadc_1 table 41 . bit descriptions for fadc_1 bits bit name description reset access [7:0] fadc_1 upper 8 - bits of 16 - bit value that defines the adc clk frequency to 1 mhz. for example, the fadc_1 and fadc_0 settings for a 32 00 mhz clk frequency would be 0x0 c and 0x 8 0 , respectively. 0x0e rw if frequency lsb register 0 address: 0x102, reset: 0x2 c , name: fif_0 table 42. b it descriptions for f if _0 bits bit name description reset access [7:0] fif_0 lower 8 - bits of 16 - bit value that defines the target if frequency to 1 mhz resolution. for example, the fif_1 and fif_0 settings for a 300 mhz if frequency would be 0x01 and 0x2c , respectively. 0x2c rw rev. 0 | page 65 of 86
AD6676 data sheet if frequency msb register 1 address: 0x103, reset: 0x01 , name: fif_1 table 43 . bit descriptions for f0_1 bits bit name description reset access [7:0] fif_1 upper 8 - bits of 16 - bit value that defines the target if frequency to 1 mhz resolution. for example, the fif_1 and fif_0 settings for a 300 mhz if frequency would be 0x01 and 0x2c , respectively. 0x01 rw bw lsb register 0 address: 0x104, reset: 0x3c , name: bw_0 table 44 . bit descriptio ns for bw_0 bits bit name description reset access [7:0] bw_0 lower 8 - bits of 16 - bit value that defines the target bw frequency to 1 mhz resolution. for example, the bw_1 and bw_0 settings for a 60 mhz bw would be 0x00 and 0x3c , respectively. 0x3c rw bw msb register 1 address: 0x105, reset: 0x00, name: bw_1 table 45 . bit descriptions for bw_1 bits bit name description reset access [7:0] bw_1 upper 8 - bits of 16 - bit value that defines the target bw frequency to 1 mhz resolution. this register should be kept to 0x00 default setting because maximum bw should be no greater than 160 mhz. 0x00 rw external inductance value register address: 0x106, reset: 0x14, name: lext table 4 6 . bit descriptions for lext bits bit n ame description reset access [7:0] lext external inductance in nh. enter the external inductance value for the lc tank resonator. the default value of 0x14 corresponds to 20 nh 0x14 rw bandwidth margin (low end) register address: 0x107, reset: 0x05, nam e: mrgn_l table 47 . bit descriptions for mrgn_l bits bit name description reset access [7:0] mrgn_l an 8 - bit register defining the offset frequency (to 1 mhz resolution) to which the frequency of the lower resonator is offset from it s theoretical ideal val ue. the default setting is 5 mh z. increasing the value lowers the actual resonator frequency. 0x05 rw rev. 0 | page 66 of 86
data sheet AD6676 bandwidth margin (upper end) register address: 0x108, reset: 0x05, name: mrgn_u table 48 . bit descriptions for mrgn_u bits bit name description reset access [7:0] mrgn_u an 8 - bit register defining the offset frequency (to 1 mhz resolution) to which the frequency of the upper resonator is offset from its theoretical ideal value. the default setting is 5 m h z. in creasing the value increases the actual resonator frequency. 0x05 rw bandwidth margin (if) register address: 0x109, reset: 0x00, name: mrgn_if table 49 . bit descriptions for mrgn_if bits bit name description reset access [7:0] mrgn _if an 8 - bit register defining the offset frequency (to 1 mhz resolution) to which the frequency of the lc resonator is offset from its theoretical ideal value. the default setting is 0 m h z. increasing the value increases the actual resonator frequency. 0x 00 rw idac1 fs gain scaling register address: 0x10a, reset: 0x40, name: idac 1 _fs table 50 . bit descriptions for idac1_fs bits bit name description reset access [7:0] idac 1 _fs this parameter allows adjustment of the full - scale input power level of the adc by adjusting the full - scale current of idac1. the nominal setting of 0x40 sets idac1 fs value to 4 ma and correspond s to the largest full - scale le vel of approximately ? 3 dbm ( with the if attenuator set to 0 db.) a setting of 0x20 or 0 x10 results idac1 fs value to 2 ma or 1 ma , thus resulting in a 6 db or 12 db reduction in pin_0dbfs. settings resulting in more than 12 db reduction are not recommended. 0x40 rw calibration control register address: 0x115, reset: 0x00, name: cal_ctrl tab le 51 . bit descriptions for cal_ctrl bits bit name description reset access [7:2] reserved 0x00 rw [1:0] cal_profile adc profile to be calibrated. select one of the four adc profiles in which to store the results of the calibration . for example , to support multiple if settings, the four profiles cover all registers in the range of 0x141 to 0x145 . rw rev. 0 | page 67 of 86
AD6676 data sheet calibration command register address: 0x116, reset: 0x00, name: cal_cmd table 52 . bit descriptions for cal_cmd bits bit name description reset access [7: 6 ] reserved 0x0 rwac 5 in i t_ntf_op 0x0 rwac 4 init_jesd 0x0 rwac 3 reson1_cal 0x0 rwac 2 flash_cal 0x0 rwac 1 init_adc 0x0 rwac 0 tune_adc 0x0 rwac setting a 1 in one or more of the bits in this reg ister initiates the internal calibration. this register is cleared automatically at the end of calibration or by setting the force_end_cal bit. calibration done register address: 0x117, reset: 0x00, name: cal_done table 53 . bit descr iptions for adc_profile bits bit name description reset access [7:1] reserved 0x00 r w [0] cal_done this bit indicates that the microcontroller has completed its calibration. it is automatically cleared by a new cal_cmd. 0x0 r w adc profile selection re gister address: 0x118, reset: 0x00, name: adc_profile table 54 . bit descriptions for adc_profile bits bit name description reset access [7:2] reserved 0x00 w [1:0] adc_profile adc profile. select which one of the four adc profiles to use in operation. the user may switch between multiple profiles if calibration has taken place for each. note that the four profiles also cover register 0x141 to register 0x145 if the digital mixer settings are varied between profiles. 0x0 w force end of calibration register address: 0x11a, reset: 0x00, name: force_end_cal table 55 . bit descriptions for force_end_cal bits bit name description reset access [7:1] reserved 0x00 rw 0 force_end_cal setting this bit high and then low (two write operations) allows the user to terminate the calibration and hand control back to the spi . this spi operation should only be performed if the AD6676 fails to clear reg ister 0x116 afte r 400 ms . 0x0 rw this is a user accessible spi register only when the controller is performing a calibration. rev. 0 | page 68 of 86
data sheet AD6676 decimation mode register address: 0x140, reset: 0x01, name: dec_mode table 56 . bit descriptions for dec_mode bits bit name settings description reset access [7:3] reserved 0x00 rw [2:0] dec_mode decimation mode. 0x01 rw 001 decimate by 32 . 010 decimate by 24 . 011 decimate by 16 . 100 decimate by 12 . coarse nco tuning register address: 0x141, reset: 0 x00, name: mix1_tuning table 57 . bit descriptions for mix1_tuning bits bit name description reset access [7:6] reserved 0x0 rw [5:0] mix1_tuning m ix1 tuning. coarse downconversion frequency, in units of f ad c /64. for example, settin g bits to 000011 downconverts by f ad c (3/64). varies rw this register has four copies, one for each of the adc profiles. the default for p rofile 0 is 0x05; the default for the other profiles is 0x00. at t he default adc clock rate of 3.2 ghz ; the default p rofile 0 downconversion frequency is ( 5/64) 3.6 ghz = 25 0 mhz fine nco tuning register address: 0x142, reset: 0x00, name: mix2_tuning table 58 . bit descriptions for mix2_tuning bits bit name description reset access [7:0] mix2_t uning mix2 tuning. fine down/upconversion frequency. for decimation m ode 1 and mode 3, this two s complement number represents steps of f ad c /4096. for decimation mode 2 and mode 4, it represents steps of f ad c /3072. a positive number is a downconverion; a ne gative number is an upconversion. 0x00 rw this register has four copies, one for each of the adc profiles. the default for p rofile 0 is 0x21; the default for the other profiles is 0x00. at the default adc clock rate of 3. 2 ghz, the default p rofile 0 downc onversion frequency is ( 33 / 4096) 3. 2 ghz = 2 5.78125 mhz coarse nco initial phase register address: 0x143, reset: 0x00, name: mix1_init table 59 . bit descriptions for mix1_init bits bit name description reset access [7:6] reserved 0x0 rw [5:0] mix1_init nco1 i nitial p hase. initial phase of the coarse resolution nco after synchronization with sysref, in units of 1/64 of a cycle. 0x00 rw this register has four copies, one for each of the adc profiles. the default for p rofile 0 is 0 x00. rev. 0 | page 69 of 86
AD6676 data sheet fine nco initial phase lsb register address: 0x144, reset: 0x00, name: mix2_init_lsb table 60 . bit descriptions for mix2_init_lsb bits bit name description reset access [7:0] mix2_init_lsb nco2 i nitial p hase. initial phase of th e fine resolution nco after synchronization with sysref, in units of 1/1024 of a cycle. the two msbs of the 10 - bit value are in register 0x145. 0x00 rw this register has four copies, one for each of the adc profiles. the default for p rofile 0 is 0x00. fin e nco initial phase msb register address: 0x145, reset: 0x00, name: mix2_init_msb table 61 . bit descriptions for mix2_init_msb bits bit name description reset access [7:2] reserved 0x00 rw [1:0] mix2_init_msb nco2 i nitial p hase. in itial phase of the fine resolution nco after synchronization with sysref, in units of 1/1024 of a cycle. the l sbs of the 10 - bit value are in register 0x144. 0x0 rw this register has four copies, one for each of the adc profiles. the default for p rofile 0 is 0x00. datapath controls register address: 0x146, reset: 0x00, name: dp_ctrl table 62 . bit descriptions for dp_ctrl bits bit name description reset access [7:1] reserved 0x00 rw 0 not_2s_compl output data format: t wos complement = 0; s traight binary = 1 standby register address: 0x150, reset: 0x02, name: standby when bits in this register are set, the corresponding blocks enter a power - down state when the chip enters standby mode. table 63 . bit descriptio ns for standby bits bit name description reset access 7 reserved 0x0 rw 6 stby_vss2gen 1: power down negative supply (vss2) generator during standby. 0x0 rw 5 stby_clk_pll 1: power down main clock pll during standby. 0x0 rw 4 stby_jesd_pll 1: power do wn jesd interface pll during standby. 0x0 rw 3 stby_jesd_phy 1: power down jesd interface transmitters during standby. 0x0 rw 2 stby_framer 1: power down jesd interface framer logic during standby. 0x0 rw 1 stby_datapath 1: power down digital datapath d uring standby. 0x1 rw 0 stby_digclk 1: disable all digital clocks during standby. 0x0 rw digital power - d own register address: 0x151, reset: 0x00, name: pd_dig table 64 . bit descriptions for pd_dig bits bit name description reset ac cess [7:3] reserved 0x00 rw 2 pd_framer 1: power down jesd interface framer logic. 0x0 rw 1 pd_datapath 1: power down digital datapath. 0x0 rw rev. 0 | page 70 of 86
data sheet AD6676 bits bit name description reset ac cess 0 pd_digclk 1: power down all digital clocks. 0x0 rw standby pin control register address: 0x152, reset: 0x 00, name: pd_pin_ctrl table 65 . bit descriptions for pd_pin_ctrl bits bit name settings description reset access [7:5] reserved 0x0 rw 4 pd_pin_en enable s tandby m ode c ontrol from a gpio p in. 0x0 rw 0 use only register 2 to se lect standby mode . 1 use r egister 2 or the selected pin to select standby mode. standby mode is the logical or of the register setting and the pin state. [3:2] reserved 0x0 rw [ 1 :0] pd_pin_sel select gpio pin for standby control. 0x0 rw 00 u se agc1 for standby control . 01 use agc2 for standby control . 10 use agc3 for standby control . 11 use agc4 for standby control . attenuator mode register address: 0x180, reset: 0x00, name: atten_mode table 66 . bit de scriptions for atten_mode bits bit name description reset access [7:1] reserved 0x00 rw 0 atten_mode attenuator mode. 0x0 rw 0 = use agc2 pin to select between values in r egister 0x0181 and r egister 0x0182 . 1 = use agc1 and agc2 pins to decremen t / increment attenuation value . attenuator agc2 pi n lo w value register address: 0x181, reset: 0x0c, name: atten_value_pin0 table 67 . bit descriptions for atten_value_pin1 bits bit name description reset access [7:0] atten_value_pi n0 attenuation value to be used in atten_mode = 0 when the agc2 pin is low. valid range is from 0 (min imum atten uation ) to 27 (max imum atten uation ). value 28 to value 31 disable the attenuator. default is 12 db attenuation. 0x0c rw attenuator agc2 pin hi gh value register address: 0x182, reset: 0x0c, name: atten_value_pin1 table 68 . bit descriptions for atten_value_pin1 bits bit name description reset access [7:0] atten_value_pin1 attenuation value to be used in atten_mode = 0 when t he agc2 pin is high. valid range is from 0 (min imum atten uation ) to 27 (max imum atten uation ). value 28 to value 31 disable the attenuator. default is 12 db attenuation. 0x0c rw attenuator initialization register address: 0x183, reset: 0x00, name: atten_i nit rev. 0 | page 71 of 86
AD6676 data sheet table 69 . bit descriptions for atten_init bits bit name description reset access [7:0] atten_init initialize the attenuator value when using atten_mode = 1. 0x00 rw attenuator status register address: 0x184, reset: 0x0 c , name: atten_ctl table 70 . bit descriptions for atten_ctl bits bit name description reset access 7 att_pin read back the state of the agc2 pin. 0x0 r [6:5] reserved 0x0 rw [4:0] atten_read read back the actual attenuation value in atten_ mode. 0x00 r adc reset threshold register address: 0x188, reset: 0x0 5 , name: adcre_thrh table 71 . bit descriptions for adcre_thrh bits bit name description reset access [7:3] reserved 0x00 rw [2:0] adcre_thrh adc reset threshold. the adc r eset triggers if more than threshold out of eight consecutive adc samples have the full - scale value of 8. 0x4 rw adc reset pulse length register address: 0x189, reset: 0x0 1 , name: adcre_pulse_len table 72 . bit description s for adcre_pulse_len bits bit name description reset access [7:5] reserved 0x0 rw [4:0] adcre_pulse_len the duration of the reset pulse to the adc, (x + 1) 8/ f adc . 0x00 rw adc reset attenuation step register address: 0x18a, reset: 0x0 6 , name: atten _step_re table 73 . bit descriptions for atten_step_re bits bit name description reset access [7:5] reserved 0x0 rw [4:0] atten_step_re the size of the increase in attenuation after a reset event, in db. the attenuation is clipped t o a maximum value of 27 db. 0x00 rw adc unstable f lag c ontrol register address: 0x18f, reset: 0x00, name: adc_unstable table 74 . bit descriptions for adc_unstable bits bit name description reset access [7:2] reserved 0x00 rw 1 cl ear_unstable_flag clear unstable flag. writing a 1 to this bit clears the unstable_flag. this bit is self clearing. 0x0 rw 0 unstable_flag unstable flag. this is a sticky flag that indicates if an adc reset condition has been detected. it is cleared only by the clear_unstable_flag bit and the hardware/software resets. 0x0 r rev. 0 | page 72 of 86
data sheet AD6676 peak threshold 0 lsb register address: 0x193, reset: 0x00, name: pkthrh0_lsb table 75 . bit descriptions for pkthrh0_lsb bits bit name settings description reset access [7:0] pkthrh0_lsb peak threshold 0 lsb. 0x00 rw peak threshold 0 msb register address: 0x194, reset: 0x00, name: pkthrh0_msb table 76 . bit descriptions for pkthrh0_msb bits bit name settings description reset access [7:4] reserved 0x0 rw [3:0] pkthrh0_msb peak threshold 0 msb. 0x0 rw peak threshold 1 lsb register address: 0x195, reset: 0x00, name: pkthrh1_lsb table 77 . bit descriptions for pkthrh1_lsb bits bit name settings description reset acce ss [7:0] pkthrh1_lsb peak threshold 1 lsb. 0x00 rw peak threshold 1 msb register address: 0x196, reset: 0x00, name: pkthrh1_msb table 78 . bit descriptions for pkthrh1_msb bits bit name settings description reset access [7:4] rese rved 0x0 rw [3:0] pkthrh1_msb peak threshold 1 msb. 0x0 rw dec low threshold lsb register address: 0x197, reset: 0x00, name: lowthrh_lsb table 79 . bit descriptions for lowthrh_lsb bits bit name settings description reset access [7:0] lowthrh_lsb low threshold lsb. 0x00 rw low threshold msb register address: 0x198, reset: 0x00, name: lowthrh_msb table 80 . bit descriptions for lowthrh_msb bits bit name settings description reset access [7:4] reserved 0x 0 rw [3:0] lowthrh_msb low threshold msb. 0x0 rw rev. 0 | page 73 of 86
AD6676 data sheet dwell time mantissa register address: 0x199, reset: 0x00, name: dwell_time_mantissa table 81 . bit descriptions for dwell_time_mantissa bits bit name settings description reset acces s [7:0] dwell_time_mantissa dwell time mantissa. 0x00 rw dwell time exponent register address: 0x19a, reset: 0x00, name: dwell_time_exp table 82 . bit descriptions for dwell_time_exp bits bit name settings description reset access [7:4] reserved 0x0 rw [3:0] dwell_time_exp dwell time exponent. 0x0 rw agc flag 0 select register address: 0x19b, reset: 0x00, name: flag0_sel table 83 . bit descriptions for flag0_sel bits bit name description reset access [7: 3] reserved 0x00 rw [2:0] flag0_sel select 1 of 4 flags to output on the agc3 pin. 0x0 rw 000 = adc reset pulse . 100 = dec peak above dec t hreshold 0 . 101 = dec peak above dec t hreshold 1 . 110 = dec peak below dec low threshold for dwel l time . agc flag 1 select register address: 0x19c, reset: 0x00, name: flag1_sel table 84 . bit descriptions for flag1_sel bits bit name description reset access [7:3] reserved 0x00 rw [2:0] flag1_sel select one of four flags to output on the agc4 pin. 0x0 rw 000 = adc reset pulse . 100 = dec peak above dec t hreshold 0 . 101 = dec peak above dec t hreshold 1 . 110 = dec peak below dec low threshold for dwell time . agc flag enable register address: 0x19e, reset: 0x00, name: en_flag table 85 . bit descriptions for en_flag bits bit name description reset access [7:5] reserved 0x0 rw 4 en_or combine adc reset with peak detect. when asserted, this bit causes the adc reset pulse ( f lag s elect o pt ion 0) to be logically or - ed with one of the peak - detect flags options specified in register 0x19b or register 0x19c . 0x0 rw [3:2] reserved 0x0 rw 1 en_flag1 enable flag 1. 0x0 rw rev. 0 | page 74 of 86
data sheet AD6676 bits bit name description reset access 0 = force agc4 pin low . 1 = enable selected flag on agc 4 pin (see flag1_sel) . 0 en_flag0 enable flag 0. 0x0 rw 0 = force agc3 pin low . 1 = enable selected flag on agc3 pin (see flag0_sel) . force gpio register address: 0x1b0, reset: 0x00, name: force_gpio table 86 . bit descriptions fo r force_gpio bits bit name description reset access [7:4] reserved 0x0 rw [3:0] force_gpio force gpio use. force one or more of the pins , agc1 to agc4 , to be used as a gpio rather than any other specified use. bit 0: f orce agc 1 to be used as a gpio . bit 1: f orce agc 2 to be used as a gpio . bit 2: f orce agc 3 to be used as a gpio . bit 3: f orce agc 4 to be used as a gpio . 0x00 rw force gpio as output register address: 0x1b1, reset: 0x00, name: force_gpio_out table 87 . bit descriptions for force_gpio_out bits bit name description reset access [7:4] reserved 0x0 rw [3:0] force_gpio_out force gpio use as an output. when used in conjunction with force_gpio, configure one or more of the pins , agc1 to agc4 , to be used as a general purpose output or input. bit 0 = 1: u se agc1 as an output . bit 0 = 0: u se agc1 as an input. bit 1 = 1: u se agc2 as an output . bit 1 = 0: u se agc2 as an input. bit 2 = 1: u se agc3 as an output . bit 2 = 0: u se agc3 as an input. bit 3 = 1: u se agc4 as an output . bit 3 = 0: u se agc4 as an input. 0x00 rw force gpio value register address: 0x1b2, reset: 0x00, name: force_gpio_val table 88 . bit descriptions for force_gpio_val bits bit name description reset access [7:4] reserved 0x0 rw [3:0] for ce_gpio_val force gpio value. when used in conjunction with force_gpio and force_gpio_out, configure the state of one or more of the pins , agc1 to agc4 , when being used as a general purpose output. bit [0]: s tate of agc 1 when being used as an output. bit [ 1]: s tate of agc2 when being used as an output. bit [2]: s tate of agc3 when being used as an output. bit [3]: s tate of agc4 when being used as an outp ut. 0x00 rw rev. 0 | page 75 of 86
AD6676 data sheet gpio output status register address: 0x1b3, reset: 0x00, name: read_gpo table 89 . bit descriptions for read_gpo bits bit name description reset access [7:4] reserved 0x0 rw [3:0] read_gpo read back the status of the gpio output bits. these are the same as the external pins , agc1 through agc4 , if the gpio are enabled and c onfigured as outputs. 0x00 r gpio input status register address: 0x1b4, reset: 0x00, name: read_gpi table 90 . bit descriptions for read_gpi bits bit name description reset access [7:4] reserved 0x0 rw [3:0] read_gpi read back the status of the gpio input bits. these are the same as the external pins , agc 1 through agc4 , if the gpio are enabled and configured as inputs 0x00 r jesd204 did register address: 0x1c0, reset: 0x00, name: did table 91 . bit descriptio ns for did bits bit name description reset access [7:0] did device id 0x00 rw jesd204 bid register address: 0x1c 1 , reset: 0x 00 , name: bid table 92 . bit descriptions for bid bits bit name description reset access [7:4] reserved 0x 0 r [3:0] bid bank id 0x0 rw jesd204 l / scr register address: 0x1c3, reset: 0x00, name: l table 93 . bit descriptions for l bits bit name settings description reset access 7 scr scr parameter. 0x0 rw 0 scrambling disabled . 1 scrambling enabled . [6:5] reserved 0x0 rw [4:0] l l parameter. 0x00 rw 00000 one lane . 00001 two lanes . rev. 0 | page 76 of 86
data sheet AD6676 jesd204 f register address: 0x1c4, reset: 0x03, name: f table 94 . bit descriptions for f bits bit name settin gs description reset access [7:0] f octest per f rame per l ane. 0x03 rw 00000001 f = 2 00000011 f = 4 jesd204 k register address: 0x1c5, reset: 0x1f , name: k table 95 . bit descriptions for k bits bit name settings descrip tion reset access [7:5] reserved 0x0 rw [4:0] k frames per multiframe. number of frames per multiframe is the register value plus one. 0x1f rw jesd204 m register address: 0x1c6, reset: 0x01 , name: m table 96 . bit descriptions f or m bits bit name settings description reset access [7:0] m m. 0x01 rw 00000001 two converters (i/q data) . jesd204 s register address: 0x1c9, reset: 0x00, name: s table 97 . bit descriptions for s bits bit name settings descr iption reset access [7:5] reserved 0x0 rw [4:0] s s. 0x00 rw 00000 one sample per frame ( the only valid option) . jesd204 res1 register address: 0x1cb, reset: 0x00, name: res1 table 98 . bit descriptions for res1 bits bit na me description reset access [7:0] res1 0x00 rw jesd204 res2 register address: 0x1cc, reset: 0x00, name: res2 table 99 . bit descriptions for res2 bits bit name description reset access [7:0] res2 0x00 rw rev. 0 | page 77 of 86
AD6676 data sheet jesd204 lid0 register a ddress: 0x1d0, reset: 0x00, name: lid0 table 100 . bit descriptions for lid0 bits bit name description reset access [7:5] reserved 0x0 rw [4:0] lid0 lane id for lane 0. 0x00 rw jesd204 lid1 register address: 0x1d1, reset: 0x01, na me: lid1 table 101 . bit descriptions for lid1 bits bit name description reset access [7:5] reserved 0x0 rw [4:0] lid1 lane id for lane 1. 0x01 rw jesd204 fchk0 register address: 0x1d8, reset: 0x44, name: fchk0 table 102 . bit descriptions for fchk0 bits bit name description reset access [7:0] fchk0 checksum for lane 0. 0x44 rw jesd204 fchk1 register address: 0x1d9, reset: 0x45, name: fchk1 table 103 . bit descriptions for fchk1 bits bit name description reset access [7:0] fchk1 checksum for lane 1. 0x45 rw enable lane fifo register address: 0x1e0, reset: 0x00, name: en_lfifo table 104 . bit descriptions for en_lfifo bits bit name description reset access [7:1] re served 0x00 rw 0 en_lfifo lane f ifo enable. once the entire configuration of the framer has been completed, and the link is powered up, set this bit to start the lane fifos that manage the hand - off of data from the framer to the transmitter phy. 0x0 rw rev. 0 | page 78 of 86
data sheet AD6676 swap register address: 0x1e1, reset: 0x00, name: swap table 105 . bit descriptions for swap bits bit name settings description reset access [7:6] reserved 0x0 rw [5:4] swap_conv bit [4] swaps the source of f ramer c onverter 0 (def ault is i channel) bit [5] swaps the source of f ramer c onverter 1 (default is q channel). 0x0 rw 00 framer i nput 1 = q channel; framer i nput 0 = i channel 01 framer i nput 1 = q channel; framer i nput 0 = q channel 10 framer i nput 1 = i channel; framer i nput 0 = i channel 11 framer i nput 1 = i channel; framer i nput 0 = q channel [3:2] reserved 0x0 rw [1:0] swap_lane bit [0] swaps the source of physical output lane 0. bit [1] swaps the source of physical output lane 1. 0x0 rw 00 out put l ane 1 = f amer lane 1; output l ane 0 = f ramer l ane 0 01 output l ane 1 = f ramer lane 1; output l ane 0 = f ramer l ane 1 10 output l ane 1 = f ramer lane 0; output l ane 0 = f ramer l ane 0 11 output l ane 1 = f ramer lane 0; output l ane 0 = f ramer l ane 1 link/lane power - d own register address: 0x1e2, reset: 0x00, name: lane_pd table 106 . bit descriptions for lane_pd bits bit name description reset access [7:4] ilas_delay ilas s tart d elay. usually the ilas starts on the fir st lmfc rising edge after sync inb goes high. this value delays the ilas by the given number of lmfc periods (multiframe periods). 0x0 rw [3:2] reserved 0x0 rw [1:0] lane_pd lane power - down. bit 0 powers down transmitter phy for l ane 0. bit 1 powers dow n transmitter phy for l ane 1. 0x0 rw interface control 0 register address: 0x1e3, reset: 0x14, name: mis1 table 107 . bit descriptions for mis1 bits bit name description reset access [7:6] reserved 0x0 rw 5 test_sample_en 0 = disa ble tran s port layer test samples . 0x0 rw 1 = enable transport laye r test samples . 4 lsync_en 0 = disable lane synchronization . 0x1 rw 1 = enable lane synchronization (default) . [3:2] ilas_mode 01 = enable ilas (default) . 0x1 rw 11 = ilas al ways on ; data link layer test mode . 1 faci_disable control of f rame a lignment c haracters . 0 = enable frame alignment character insertion . 1 = disable frame alignment character insertion . 0x0 rw 0 reserved 0x0 rw rev. 0 | page 79 of 86
AD6676 data sheet interface control 1 register address : 0x1e4, reset: 0x00, name: sync_pin table 108 . bit descriptions for sync_pin bits bit name description reset access [7:6] reserved 0x0 rw 5 sync_pin_inv 0 = d o not invert sync inb pin ; syncinb is active low . 0x0 rw 1 = i nvert sy ncinb pin ; syncinb is active high . [4:2] reserved 0x0 rw 1 inv_10b 0 = d o not invert octets . 0x0 rw 1 = i nvert all bi ts in 10 - bit octets from framer. setting the bit to 1 h as the same effect as swapping the differential output data pins . 0 reser ved 0x0 rw interface test register address: 0x1e5, reset: 0x00, name: test_gen table 109 . bit descriptions for test_gen bits bit name settings description reset access [7: 6 ] reserved 0x0 rw [5:4] test_gen_sel test p oint. 0x0 r w 00 insert test data at framer input (16 bits) . 01 insert test data at phy input (10 bits) . 10 insert test data at scrambler input (8 bits) . [3:0] test_gen_mode test m ode. 0x0 rw 0000 normal mode ; test disabled . 0001 alternating c heckerboard . 0010 1/0 word toggle . 0011 long pn sequence . 0100 short pn sequence . 0101 repeating user pattern mode . 0110 single user pattern mode . 0111 ramp . 1000 modified rpat sequence . 1001 not used . 1010 jspa t sequence . 1011 jtspat sequence . ilas count register address: 0x1e6, reset: 0x00, name: kf_ilas table 110 . bit descriptions for kf_ilas bits bit name description reset access [7:0] kf_ilas initial lane assignment sequence c ount. the ilas is transmitted (kf_ilas + 1) times. 0x00 rw rev. 0 | page 80 of 86
data sheet AD6676 sync inb and sysref control register address: 0x1e7, reset: 0x00, name: sync in b_ctrl table 111 . bit descriptions for syncb_ctrl bits bit name description reset access [7:4] reserved 0x0 rw 3 pd_sysref_rx power down sysref receiver. 0x0 rw 2 lvds_sync inb use lvds for sync inb . (0 = cmos, 1 = lvds differential with 100 ? termination) . 0x0 rw [1:0] reserved 0x0 rw clock synchronization register address: 0x1e8, reset: 0x00, name: mix_ctrl table 112 . bit descriptions for mix_ctrl bits bit name description reset access 7 reserved 0x0 rw 6 mix_use _2nd when used in conjunction with b it 5, setting this bit causes the second sysref that is used to align the clocks to also be used to reset the mixer nco phases. this bit does not self - clear. this bit is only active when b it 2 is also active. 0x0 rw 5 m ix_next once set, only the next sysref pulse that is used to align the clock dividers i s also used to reset the mixers nco phases. this bit self clears after use. this bit is only active when b it 1 is also active. 0x0 rwac 4 mix_all any sysref that is use d to align the clocks will also be used to reset the mixers' nco phases. this bit is only active when b it 0 is also active. 0x0 rw 3 reserved 0x0 rw 2 use_2nd_sysref when used in conjunction with bit 1, setting this bit causes the second sysref to be us ed for alignment rather than the first. this bit does not self clear. 0x0 rw 1 next_sysref once set, only the next sysref pulse is used to align the clock dividers. this bit self - clears after the next sysref. 0x0 rwac 0 all_sysref all sysref pulses are u sed to align the clock dividers. 0x0 rw lmfc offset register address: 0x1e9, reset: 0x00, name: k_offset table 113 . bit descriptions for k_offset bits bit name description reset access [7:5] reserved 0x0 rw [4:0] k_offset this re gister provides an offset that moves the position of the internal lmfc with respect to sysref. a larger value places the lmfc later in time. in units of frame periods. 0x00 rw rev. 0 | page 81 of 86
AD6676 data sheet sysref window register address: 0x1ea, reset: 0x00, name: sysref table 114 . bit descriptions for sysref bits bit name description reset access [7:4] sysref_win_neg sysref_win_neg. do not align clocks if sysref is no earlier than register value before its expected position. in units of 2/ f adc . 0x0 rw [3:0] sys ref_win_pos sysref_win_pos. do not align clocks if sysref is no later than register value after its expected position. in units of 2/ f adc . 0x0 rw phy control 0 register address: 0x1eb, reset: 0x1c, name: ser1 table 115 . bit descript ions for ser1 bits bit name description reset access 7 ser_drv_ps serializer polarity selection. 0x0 rw 0 = polarity not inverted . 1 = polarity inverted . [6:0] reserved 0x1c rw phy control 3 register address: 0x1ef, reset: 0x00, name: pre -em phasis table 116 . bit descriptions for pre - emphasis bits bit name description reset access 7 ser_emp_ps1 toggle p olarity of lane 1 e mphasis. 0x0 rw [6:4] ser_emp_idac1 lane 1 idac setting. 00: 0 mv emphasis differential p - p . 0x0 rw 01: 160 mv emphasis differential p -p . 10: 80 mv emphasis differential p -p . 11: 40 mv emphasis differential p -p . 3 ser_emp_ps0 toggle polarity of lane 0 emphasis. 0x0 rw [ 2:0 ] ser_emp_idac0 lane 0 idac setting. 00: 0 mv emphasis differential p - p . 0x0 rw 01: 160 mv emphasis differential p -p . 10: 80 mv emphasis differential p -p . 11: 40 mv emphasis differential p -p . adc standby 0 register address: 0x250, reset: 0xff, name: stby_ dac table 117 . bit descriptions for stby_ dac bit s bit name description reset access [7:0] stby_dac setting register to 0x95 res ults in faster stand by adc recovery time. 0xff rw rev. 0 | page 82 of 86
data sheet AD6676 clksyn enable register address: 0x2a0, reset: 0x00, name: clksyn_enable table 118 . bit descriptions fo r clksyn_enalbe bits bit name description reset access 7 en_extck extck e nable. 0x0 rw 6 en_adc_ck adc ck e nable. 0x0 rw 5 en_synth synthesizer e nable. 0x0 rw 4 en_vco_ptat vco ptat e nable. 0x0 rw 3 en_vco_alc vco alc e nable. 0x0 rw 2 en_vco vco e nab le. 0x0 rw 1 en_overide_cal ove r ride calibration e nable. 0x0 rw 0 en_overide ove r ride e nable. 0x0 rw clksyn integer n lsb register address: 0x2a1, reset: 0x 80 , name: clksyn_int_n_lsb table 119 . bit descriptions for clksyn_int_n_ls b bits bit name description reset access [7:0] int_n_lsb lower lsbs of 11 - bit integer-n v alue . 0x0 rw clksyn integer n msb register address: 0x2a2, reset: 0x00, name: clksyn_int_n_msb table 120 . bit descriptions for clksyn_int_n_ms b bits bit name description reset access [7:3] reserved 0x0 rw [2:0] int_n_msb upper 3 m sbs of 11 - bit integer n v alue . 0x0 rw clksyn vco calibration reset register address: 0x2a5, reset: 0x00, name: vco_cal_reset table 121 . bit d escriptions for vco_cal_reset bits bit name description reset access [7:4] reserved 0x0 rw 3 vco_cal_reset reset vco c alibration . 0 rw [2:0] reserved 0x0 rw clksyn vco b ias r egister address: 0x2aa, reset: 0x 37 , name: clksyn_vco_bias table 122 . bit descriptions for clksyn_vco_bias bits bit name description reset access [7:6] reserved 0 rw [5:4] bias_tempco vco bias tempco setting . 0x0 rw 3 reserved 0 rw [2:0] bias vco bias setting . 0x4 rw rev. 0 | page 83 of 86
AD6676 data sheet clksyn vco calibration registe r address: 0x2ab, reset: 0xc0, name: clksyn_vco_cal table 123 . bit descriptions for clksyn_vco_cal bits bit name description reset access [7:4] ini t _alc_value initial automatic level control value . 0xc rw 3 alc_dis alc calibration t est b it . 0 rw [2:1] reserved 0 rw 0 id_synth initiates vco c alibration . 0 rw clksyn charge pump register address: 0x2ac, reset: 0x 19 , name: clksyn_i_cp table 124 . bit descriptions for clksyn_i_cp bits bit name description reset a ccess [7:6] reserved 0x0 rw [5:0] i_cp charge pump current = min(63, 1. 33x10 28 /( f pfd f c l k 2 ) - 1). 0x0 rw clksyn charge pump calibration register address: 0x2ad, reset: 0x00, name: en_cp_cal table 125 . bit descriptions for en_cp_ cal bits bit name description reset access [7:6] en_cp_cal 0x0 rw [6:0] reserved 0x0 rw clksyn vco varactor register address: 0x2b7, reset: 0x d 0, name: clksyn_vco_var table 126 . bit descriptions for clksyn_ vco_var bits bit name description reset access [7:4] vco_var vco varactor setting . 0xe0 rw [3:0] reserved clksyn reference divider and sysref control register address: 0x2bb, reset: 0x39, name: clksyn_r_div table 127 . bit descriptions for clksyn_ r _div bits bit name description reset access [7:6] r_div 00 = div -by -1; 01= div -by -2; 10 = div -by -4; 11 = multiply -by -2. 00 rw [5: 4 ] reserved 11 rw 3 sysref_ctrl sysref i nput s ampling c lock. 0 = u se clock s ynthesizer r efer ence c lock . 1 = u se internal clock at f ad c /2 (use for nonclock synthesizer case) . 1 rw 1 clkin_imped clkin impedance. 0 = configure clk as 100 ? termination, configuration for clock synthesizer disabled. 1 = configure clk+ as high - z, configuration for clock synthesizer enabled. 0 rw [1 :0] reserved 01 rw rev. 0 | page 84 of 86
data sheet AD6676 rev. 0 | page 85 of 86 clksyn status register address: 0x2bc, reset: 0x00, name: clksyn_status table 128. bit descriptions for clksyn_status bits bit name description reset access 3 pll_lck clock synthesizer lock bit (1 = lock). 0x0 r 1 vco cal busy vco calibration busy (0 = done). 0x0 r 0 cp cal done charge pump calibration done (1 = done). 0x0 r jesdsyn status register address: 0x2dc, reset: 0x00, name: jesdsyn_status table 129. bit descriptions for jesdsyn_status bits bit name description reset access [7:4] reserved 0x0 r 3 pll_lck jesd204 pll synthesizer lock bit (1 = lock). 0x0 r [2:0] reserved shuffler control register address: 0x340, reset: 0x03, name: shuffle_ctrl table 130. bit descriptions for shuffle_ctrl bits bit name description reset access [7:1] reserved 0x00 rw 0 en_adaptive_shuffle enable adaptive flash shuffling. 0x0 rw shuffler threshold 1 and 2 register address: 0x342, reset: 0xf5, name: shuffle_threg_0 table 131. bit descriptions for shuffle_threg_0 bits bit name description reset access [7:4] shuffle_th2 threshold value for shuffling every two cycles. shuffle-every-2 is triggered when the adc data is greater than or equal to this threshold. 0x0 r [3:0] shuffle_th1 threshold value for shuffling every one cycle. shuffle-every-1 is triggered when the adc data is greater th an or equal to this threshold 0x0 r shuffler threshold 3 and 4 register address: 0x343, reset: 0xff, name: shuffle_threg_1 table 132. bit descriptions for shuffle_threg_1 bits bit name description reset access [7:4] shuffle_th4 threshold value for shuffling every four cycles. shuffle-every-4 is triggered when the adc data is greater than or equal to this threshold. 0x0 r [3:0] shuffle_th3 threshold value for shuffling every thr ee cycles. shuffle-every-3 is triggered when the adc data is greater th an or equal to this threshold 0x0 r
AD6676 data sheet outline dimensions 03-14-2013- a a b c d e f g h j k 0.660 0.600 0.540 4.33 4.29 4.25 5.08 5.04 5.00 bot t om view (bal l side up) t op view (bal l side down) side view 0.270 0.240 0.210 0.390 0.360 0.330 0.360 0.320 0.280 4.50 ref 3.50 ref 0.50 bal l pitch 0.36 0.27 0.43 bal l a1 identifier 1 2 3 4 5 6 7 8 coplanarity 0.05 sea ting plane figure 149 . 80 - ball wafer level chip scale package [wlcsp] (cb - 80 - 5) dimensions shown in millimeters ordering guide model 1 tem perature range package description package option AD6676 bcbzrl ?40c to +85c 80 - ball wafer level chip scale package [wlcsp] cb - 80 - 5 AD6676 ebz evaluation board 1 z = rohs compliant part. ? 2014 analog devices, inc. all right s reserved. trademarks and registered trademarks are the property of their respective owners. d12348 - 0- 10/14(0) rev. 0 | page 86 of 86

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